target/riscv/cpu.h

2  * QEMU RISC-V CPU
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
25 #include "hw/qdev-properties.h"
26 #include "exec/cpu-common.h"
27 #include "exec/cpu-defs.h"
28 #include "exec/cpu-interrupt.h"
30 #include "qemu/cpu-float.h"
35 #include "qapi/qapi-types-common.h"
36 #include "cpu-qom.h"
53 #define RV(x) ((target_ulong)1 << (x - 'A'))
92 #define RISCV_PROFILE_EXT_LIST_END -1
93 #define RISCV_PROFILE_ATTR_UNUSED -1
102 enum {
114 enum {
122 typedef enum {
129 /* Enum holds PMM field values for Zjpm v1.0 extension */
130 typedef enum {
141      * This enhancement is only available in system-mode QEMU,
143      * the SMP cores in user-mode QEMU.
158 #define RISCV_IMPLIED_EXTS_RULE_END -1
178 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
204     target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
219     /* Floating-Point state */
238     /* 128-bit helpers upper part return value */
268      * For RV32 this is 32-bit mstatus and 32-bit mstatush.
269      * For RV64 this is a 64-bit mstatus.
276      * external interrupt value. The MIP register is always up-to-date.
300     target_ulong satp;   /* since: priv-1.10.0 */
311     target_ulong mtval;  /* since: priv-1.10.0 */
356     /* Upper 64-bits of 128-bit CSRs */
362      * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
363      * For RV64 this is a 64-bit vsstatus.
373     /* AIA VS-mode CSRs */
389      * Signals whether the current exception occurred with two-stage address
394      * Signals whether the current exception occurred while doing two-stage
395      * address translation for the VS-stage page table walk.
450     /* machine specific AIA ireg read-modify-write callback */
476     QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
477     QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
495     target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */
503  * map is a 16-bit bitmap: the most significant set bit in map is the maximum
508  * init is a 16-bit bitmap used to make sure the user selected a correct
571     return (env->misa_ext & ext) != 0;  in riscv_has_ext()
580 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
628 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
645     enum CTRType type, target_ulong prev_priv, bool prev_virt);
695     return env->misa_mxl;
702     return &env_archcpu(env)->cfg;  in riscv_cpu_cfg()
708     int mode = env->priv;  in cpu_address_mode()
710     if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {  in cpu_address_mode()
711         mode = get_field(env->mstatus, MSTATUS_MPP);  in cpu_address_mode()
718     RISCVMXL xl = env->misa_mxl;  in cpu_get_xl()
720      * When emulating a 32-bit-only cpu, use RV32.  in cpu_get_xl()
721      * When emulating a 64-bit cpu, and MXL has been reduced to RV32,  in cpu_get_xl()
730             xl = get_field(env->mstatus, MSTATUS64_UXL);  in cpu_get_xl()
733             xl = get_field(env->mstatus, MSTATUS64_SXL);  in cpu_get_xl()
747     return cpu_get_xl(env, env->priv);  in cpu_recompute_xl()
749     return env->misa_mxl;  in cpu_recompute_xl()
760     return env->xl;  in cpu_address_xl()
771     return 16 << env->xl;  in riscv_cpu_xlen()
780     return env->misa_mxl;  in riscv_cpu_sxl()
782     if (env->misa_mxl != MXL_RV32) {  in riscv_cpu_sxl()
783         return get_field(env->mstatus, MSTATUS64_SXL);  in riscv_cpu_sxl()
796         return cfg->ext_zca;  in riscv_cpu_allow_16bit_insn()
809  *      -       100       -
810  *     1/8      101      -3
811  *     1/4      110      -2
812  *     1/2      111      -1
814  * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul)
816  *      => VLMAX = vlen >> (1 + 3 - (-3))
830     return vlen >> (vsew + 3 - lmul);  in vext_get_vlmax()
906 enum {
915 enum riscv_pmu_event_idx {
923 /* used by tcg/tcg-cpu.c*/