366     return 16 << mcc->def->misa_mxl_max;  in riscv_cpu_max_xlen()
695     env->misa_mxl = mcc->def->misa_mxl_max;  in riscv_cpu_reset_hold()
1092     env->misa_mxl = mcc->def->misa_mxl_max;  in riscv_cpu_init()
1110     RISCV_CPU(obj)->cfg.ext_zicntr = !mcc->def->bare;  in riscv_cpu_init()
1111     RISCV_CPU(obj)->cfg.ext_zihpm = !mcc->def->bare;  in riscv_cpu_init()
1123     if (mcc->def->profile) {  in riscv_cpu_init()
1124         mcc->def->profile->enabled = true;  in riscv_cpu_init()
1127     env->misa_ext_mask = env->misa_ext = mcc->def->misa_ext;  in riscv_cpu_init()
1128     riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg);  in riscv_cpu_init()
1130     if (mcc->def->priv_spec != RISCV_PROFILE_ATTR_UNUSED) {  in riscv_cpu_init()
1131         cpu->env.priv_ver = mcc->def->priv_spec;  in riscv_cpu_init()
1133     if (mcc->def->vext_spec != RISCV_PROFILE_ATTR_UNUSED) {  in riscv_cpu_init()
1134         cpu->env.vext_ver = mcc->def->vext_spec;  in riscv_cpu_init()
1137     if (mcc->def->custom_csrs) {  in riscv_cpu_init()
1138         riscv_register_custom_csrs(cpu, mcc->def->custom_csrs);  in riscv_cpu_init()
1177     switch (mcc->def->misa_mxl_max) {  in riscv_cpu_validate_misa_mxl()
2705     if (pcc->def) {  in riscv_cpu_class_base_init()
2706         mcc->def = g_memdup2(pcc->def, sizeof(*pcc->def));  in riscv_cpu_class_base_init()
2708         mcc->def = g_new0(RISCVCPUDef, 1);  in riscv_cpu_class_base_init()
2712         const RISCVCPUDef *def = data;  in riscv_cpu_class_base_init()  local
2713         mcc->def->bare |= def->bare;  in riscv_cpu_class_base_init()
2714         if (def->profile) {  in riscv_cpu_class_base_init()
2715             assert(profile_extends(def->profile, mcc->def->profile));  in riscv_cpu_class_base_init()
2716             assert(mcc->def->bare);  in riscv_cpu_class_base_init()
2717             mcc->def->profile = def->profile;  in riscv_cpu_class_base_init()
2719         if (def->misa_mxl_max) {  in riscv_cpu_class_base_init()
2720             assert(def->misa_mxl_max <= MXL_RV128);  in riscv_cpu_class_base_init()
2721             mcc->def->misa_mxl_max = def->misa_mxl_max;  in riscv_cpu_class_base_init()
2728             if (mcc->def->misa_mxl_max == MXL_RV32 &&  in riscv_cpu_class_base_init()
2729                 !valid_vm_1_10_32[mcc->def->cfg.max_satp_mode]) {  in riscv_cpu_class_base_init()
2730                 mcc->def->cfg.max_satp_mode = VM_1_10_SV32;  in riscv_cpu_class_base_init()
2734         if (def->priv_spec != RISCV_PROFILE_ATTR_UNUSED) {  in riscv_cpu_class_base_init()
2735             assert(def->priv_spec <= PRIV_VERSION_LATEST);  in riscv_cpu_class_base_init()
2736             mcc->def->priv_spec = def->priv_spec;  in riscv_cpu_class_base_init()
2738         if (def->vext_spec != RISCV_PROFILE_ATTR_UNUSED) {  in riscv_cpu_class_base_init()
2739             assert(def->vext_spec != 0);  in riscv_cpu_class_base_init()
2740             mcc->def->vext_spec = def->vext_spec;  in riscv_cpu_class_base_init()
2742         mcc->def->misa_ext |= def->misa_ext;  in riscv_cpu_class_base_init()
2744         riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg);  in riscv_cpu_class_base_init()
2746         if (def->custom_csrs) {  in riscv_cpu_class_base_init()
2747             assert(!mcc->def->custom_csrs);  in riscv_cpu_class_base_init()
2748             mcc->def->custom_csrs = def->custom_csrs;  in riscv_cpu_class_base_init()