Lines Matching +full:lock +full:- +full:pr
4 * Copyright (c) 2003-2007 Jocelyn Mayer
20 #include "qemu/main-loop.h"
23 #include "accel/tcg/cpu-ldst.h"
24 #include "exec/helper-proto.h"
41 cs->exception_index = exception; in raise_exception_err_ra()
42 env->error_code = error_code; in raise_exception_err_ra()
107 for (int i = 3; i >= 0; i--) { in helper_SIMON_LIKE_32_64()
115 z = (z0 >> (63 - i)) & 1; in helper_SIMON_LIKE_32_64()
175 #include "qemu/guest-random.h"
182 if (env->msr & R_MSR_PR_MASK) { \
183 if (!(env->spr[SPR_DEXCR] & R_DEXCR_PRO_##dexcr_aspect##_MASK || \
184 env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
186 } else if (!(env->msr & R_MSR_HV_MASK)) { \
187 if (!(env->spr[SPR_DEXCR] & R_DEXCR_PNH_##dexcr_aspect##_MASK || \
188 env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
190 } else if (!(env->msr & R_MSR_S_MASK)) { \
191 if (!(env->spr[SPR_HDEXCR] & R_HDEXCR_HNU_##dexcr_aspect##_MASK)) \
206 HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true, NPHIE)
207 HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false, NPHIE)
208 HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true, PHIE)
209 HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false, PHIE)
222 insn = ppc_ldl_code(env, env->nip); in ppc_cpu_do_unaligned_access()
224 switch (env->mmu_model) { in ppc_cpu_do_unaligned_access()
226 env->spr[SPR_40x_DEAR] = vaddr; in ppc_cpu_do_unaligned_access()
230 env->spr[SPR_BOOKE_DEAR] = vaddr; in ppc_cpu_do_unaligned_access()
233 env->spr[SPR_DAR] = vaddr; in ppc_cpu_do_unaligned_access()
237 cs->exception_index = POWERPC_EXCP_ALIGN; in ppc_cpu_do_unaligned_access()
238 env->error_code = insn & 0x03FF0000; in ppc_cpu_do_unaligned_access()
250 switch (env->excp_model) { in ppc_cpu_do_transaction_failed()
261 env->spr[SPR_DAR] = vaddr; in ppc_cpu_do_transaction_failed()
262 env->spr[SPR_DSISR] = PPC_BIT(57); in ppc_cpu_do_transaction_failed()
263 env->error_code = PPC_BIT(42); in ppc_cpu_do_transaction_failed()
270 env->spr[SPR_DAR] = vaddr; in ppc_cpu_do_transaction_failed()
271 env->error_code = PPC_BIT(36) | PPC_BIT(43) | PPC_BIT(45); in ppc_cpu_do_transaction_failed()
272 env->error_code |= PPC_BIT(42); in ppc_cpu_do_transaction_failed()
279 env->error_code = PPC_BIT(36) | PPC_BIT(44) | PPC_BIT(45); in ppc_cpu_do_transaction_failed()
291 cs->exception_index = POWERPC_EXCP_MCHECK; in ppc_cpu_do_transaction_failed()
300 if (env->insns_flags2 & PPC2_ISA207S) { in ppc_cpu_debug_excp_handler()
301 if (cs->watchpoint_hit) { in ppc_cpu_debug_excp_handler()
302 if (cs->watchpoint_hit->flags & BP_CPU) { in ppc_cpu_debug_excp_handler()
303 env->spr[SPR_DAR] = cs->watchpoint_hit->hitaddr; in ppc_cpu_debug_excp_handler()
304 env->spr[SPR_DSISR] = PPC_BIT(41); in ppc_cpu_debug_excp_handler()
305 cs->watchpoint_hit = NULL; in ppc_cpu_debug_excp_handler()
308 cs->watchpoint_hit = NULL; in ppc_cpu_debug_excp_handler()
309 } else if (cpu_breakpoint_test(cs, env->nip, BP_CPU)) { in ppc_cpu_debug_excp_handler()
322 if (env->insns_flags2 & PPC2_ISA207S) { in ppc_cpu_debug_check_breakpoint()
325 priv = env->spr[SPR_CIABR] & PPC_BITMASK(62, 63); in ppc_cpu_debug_check_breakpoint()
328 return env->msr & ((target_ulong)1 << MSR_PR); in ppc_cpu_debug_check_breakpoint()
330 return (!(env->msr & ((target_ulong)1 << MSR_PR)) && in ppc_cpu_debug_check_breakpoint()
331 !(env->msr & ((target_ulong)1 << MSR_HV))); in ppc_cpu_debug_check_breakpoint()
333 return (!(env->msr & ((target_ulong)1 << MSR_PR)) && in ppc_cpu_debug_check_breakpoint()
334 (env->msr & ((target_ulong)1 << MSR_HV))); in ppc_cpu_debug_check_breakpoint()
348 bool wt, wti, hv, sv, pr; in ppc_cpu_debug_check_watchpoint() local
351 if ((env->insns_flags2 & PPC2_ISA207S) && in ppc_cpu_debug_check_watchpoint()
352 (wp == env->dawr_watchpoint[0])) { in ppc_cpu_debug_check_watchpoint()
353 dawrx = env->spr[SPR_DAWRX0]; in ppc_cpu_debug_check_watchpoint()
354 } else if ((env->insns_flags2 & PPC2_ISA310) && in ppc_cpu_debug_check_watchpoint()
355 (wp == env->dawr_watchpoint[1])) { in ppc_cpu_debug_check_watchpoint()
356 dawrx = env->spr[SPR_DAWRX1]; in ppc_cpu_debug_check_watchpoint()
365 pr = extract32(dawrx, PPC_BIT_NR(62), 1); in ppc_cpu_debug_check_watchpoint()
367 if ((env->msr & ((target_ulong)1 << MSR_PR)) && !pr) { in ppc_cpu_debug_check_watchpoint()
369 } else if ((env->msr & ((target_ulong)1 << MSR_HV)) && !hv) { in ppc_cpu_debug_check_watchpoint()
376 if (env->msr & ((target_ulong)1 << MSR_DR)) { in ppc_cpu_debug_check_watchpoint()
419 return !!(env->msr & ((target_ulong)1 << MSR_LE)); in insn_need_byteswap()
437 if ((*env->check_attn)(env)) { in helper_attn()
447 if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) { in helper_scv()
458 cs->halted = 1; in helper_pminsn()
461 env->resume_as_sreset = (insn != PPC_PM_STOP) || in helper_pminsn()
462 (env->spr[SPR_PSSCR] & PSSCR_EC); in helper_pminsn()
465 if (env->resume_as_sreset) { in helper_pminsn()
495 if (env->flags & POWERPC_FLAG_TGPR) { in do_rfi()
500 /* Switching to 32-bit ? Crop the nip */ in do_rfi()
508 env->nip = nip & ~((target_ulong)0x00000003); in do_rfi()
510 trace_ppc_excp_rfi(env->nip, env->msr); in do_rfi()
517 env->reserve_addr = -1; in do_rfi()
525 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); in helper_rfi()
537 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); in helper_rfid()
542 do_rfi(env, env->lr, env->ctr); in helper_rfscv()
547 do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); in helper_hrfid()
552 target_ulong msr = env->msr; in helper_rfebb()
560 if (env->spr[SPR_BESCR] & BESCR_INVALID) { in helper_rfebb()
565 env->nip = env->spr[SPR_EBBRR]; in helper_rfebb()
567 /* Switching to 32-bit ? Crop the nip */ in helper_rfebb()
569 env->nip = (uint32_t)env->spr[SPR_EBBRR]; in helper_rfebb()
573 env->spr[SPR_BESCR] |= BESCR_GE; in helper_rfebb()
575 env->spr[SPR_BESCR] &= ~BESCR_GE; in helper_rfebb()
600 env->spr[SPR_BESCR] |= BESCR_PMEO; in do_ebb()
602 env->spr[SPR_BESCR] |= BESCR_EEO; in do_ebb()
605 if (FIELD_EX64(env->msr, MSR, PR)) { in do_ebb()
614 bool perfm_ebb_enabled = env->spr[SPR_POWER_MMCR0] & MMCR0_EBE && in raise_ebb_perfm_exception()
615 env->spr[SPR_BESCR] & BESCR_PME && in raise_ebb_perfm_exception()
616 env->spr[SPR_BESCR] & BESCR_GE; in raise_ebb_perfm_exception()
630 do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]); in helper_40x_rfci()
635 do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]); in helper_rfci()
641 do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]); in helper_rfdi()
647 do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); in helper_rfmci()
654 int irq = -1; in dbell2irq()
698 CPUPPCState *cenv = &cpu->env; in helper_msgsnd()
700 if ((rb & DBELL_BRDCAST_MASK) || (cenv->spr[SPR_BOOKE_PIR] == pir)) { in helper_msgsnd()
714 * instruction is a no-op in dbell_type_server()
778 if (!(env->insns_flags2 & PPC2_ISA300)) { in helper_book3s_msgsnd()
791 (env->flags & POWERPC_FLAG_SMT_1LPAR))) { in helper_book3s_msgsnd()
802 * irq handling needs it, but ppc_set_irq takes the lock itself if needed, in helper_book3s_msgsnd()
826 * multi-threaded processor
840 /* Single-step tracing */
844 if (env->insns_flags2 & PPC2_ISA207S) { in helper_book3s_trace()
846 env->spr[SPR_POWER_SIAR] = prev_ip; in helper_book3s_trace()