Lines Matching full:1
41 tmp = env->gpr[1]; in hreg_swap_gpr_tgpr()
42 env->gpr[1] = env->tgpr[1]; in hreg_swap_gpr_tgpr()
43 env->tgpr[1] = tmp; in hreg_swap_gpr_tgpr()
55 bool pr = !!(env->msr & (1 << MSR_PR)); in hreg_check_bhrb_enable()
70 hv = !!(env->msr & (1ull << MSR_HV)); in hreg_check_bhrb_enable()
92 hflags |= 1 << HFLAGS_PMCC0; in hreg_compute_pmu_hflags_value()
95 hflags |= 1 << HFLAGS_PMCC1; in hreg_compute_pmu_hflags_value()
98 hflags |= 1 << HFLAGS_PMCJCE; in hreg_compute_pmu_hflags_value()
101 hflags |= 1 << HFLAGS_BHRB_ENABLE; in hreg_compute_pmu_hflags_value()
106 hflags |= 1 << HFLAGS_INSN_CNT; in hreg_compute_pmu_hflags_value()
108 hflags |= 1 << HFLAGS_PMC_OTHER; in hreg_compute_pmu_hflags_value()
122 hflags_mask |= 1 << HFLAGS_PMCC0; in hreg_compute_pmu_hflags_mask()
123 hflags_mask |= 1 << HFLAGS_PMCC1; in hreg_compute_pmu_hflags_mask()
124 hflags_mask |= 1 << HFLAGS_PMCJCE; in hreg_compute_pmu_hflags_mask()
125 hflags_mask |= 1 << HFLAGS_INSN_CNT; in hreg_compute_pmu_hflags_mask()
126 hflags_mask |= 1 << HFLAGS_PMC_OTHER; in hreg_compute_pmu_hflags_mask()
127 hflags_mask |= 1 << HFLAGS_BHRB_ENABLE; in hreg_compute_pmu_hflags_mask()
144 msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | in hreg_compute_hflags_value()
145 (1 << MSR_DR) | (1 << MSR_FP)); in hreg_compute_hflags_value()
150 hflags |= 1 << HFLAGS_SE; in hreg_compute_hflags_value()
153 hflags |= 1 << HFLAGS_BE; in hreg_compute_hflags_value()
158 msr_mask |= 1 << MSR_BE; in hreg_compute_hflags_value()
162 msr_mask |= 1 << MSR_SE; in hreg_compute_hflags_value()
167 hflags |= 1 << HFLAGS_64; in hreg_compute_hflags_value()
169 if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) { in hreg_compute_hflags_value()
170 hflags |= 1 << HFLAGS_SPE; in hreg_compute_hflags_value()
174 msr_mask |= 1 << MSR_VR; in hreg_compute_hflags_value()
178 msr_mask |= 1 << MSR_VSX; in hreg_compute_hflags_value()
180 if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { in hreg_compute_hflags_value()
181 hflags |= 1 << HFLAGS_TM; in hreg_compute_hflags_value()
184 hflags |= 1 << HFLAGS_GTSE; in hreg_compute_hflags_value()
187 hflags |= 1 << HFLAGS_HR; in hreg_compute_hflags_value()
191 if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { in hreg_compute_hflags_value()
192 hflags |= 1 << HFLAGS_HV; in hreg_compute_hflags_value()
202 * 1 = Guest Kernel space virtual mode in hreg_compute_hflags_value()
213 * 1 = AS 0 HV Kernel space in hreg_compute_hflags_value()
214 * 2 = AS 1 HV User space in hreg_compute_hflags_value()
215 * 3 = AS 1 HV Kernel space in hreg_compute_hflags_value()
218 * 6 = AS 1 Guest User space in hreg_compute_hflags_value()
219 * 7 = AS 1 Guest Kernel space in hreg_compute_hflags_value()
222 dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1; in hreg_compute_hflags_value()
225 dmmu_idx |= msr & (1 << MSR_GS) ? 4 : 0; in hreg_compute_hflags_value()
227 immu_idx |= msr & (1 << MSR_IS) ? 2 : 0; in hreg_compute_hflags_value()
228 dmmu_idx |= msr & (1 << MSR_DS) ? 2 : 0; in hreg_compute_hflags_value()
230 dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0; in hreg_compute_hflags_value()
232 immu_idx |= msr & (1 << MSR_IR) ? 0 : 2; in hreg_compute_hflags_value()
233 dmmu_idx |= msr & (1 << MSR_DR) ? 0 : 2; in hreg_compute_hflags_value()
306 value &= ~(1 << MSR_ME); in hreg_store_msr()
307 value |= env->msr & (1 << MSR_ME); in hreg_store_msr()
318 ((value ^ env->msr) & (1 << MSR_TGPR)))) { in hreg_store_msr()
326 * If PR=1 then EE, IR and DR must be 1 in hreg_store_msr()
330 * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS in hreg_store_msr()
335 if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { in hreg_store_msr()
336 value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); in hreg_store_msr()
346 cs->halted = 1; in hreg_store_msr()
560 /* Storage Description Register 1 */