Lines Matching +full:- +full:- +full:-
4 * Copyright (c) 2003-2007 Jocelyn Mayer
20 #include "qemu/main-loop.h"
116 ppc_dump_gpr(env, 8), env->nip); in dump_syscall()
131 env->nip); in dump_hcall()
147 miss = &env->spr[SPR_IMISS]; in ppc_excp_debug_sw_tlb()
148 cmp = &env->spr[SPR_ICMP]; in ppc_excp_debug_sw_tlb()
156 miss = &env->spr[SPR_DMISS]; in ppc_excp_debug_sw_tlb()
157 cmp = &env->spr[SPR_DCMP]; in ppc_excp_debug_sw_tlb()
162 env->spr[SPR_HASH1], env->spr[SPR_HASH2], in ppc_excp_debug_sw_tlb()
163 env->error_code); in ppc_excp_debug_sw_tlb()
170 env->resume_as_sreset = false; in powerpc_reset_wakeup()
209 * AIL - Alternate Interrupt Location, a mode that allows interrupts to be
219 * a SLB multi-hit which requires SLB flush before the MMU can be enabled).
227 * +-----------+-------------+---------+-------------+-----+
232 * +-------------------------------------------------------+
236 * +-----------+-------------+---------+-------------+-----+
239 * +-------------------------------------------------------+
241 * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be sent to
245 * interrupts (MSR[HV] 0->0) from using AIL if the hypervisor does not want to
246 * use AIL for its MSR[HV] 0->1 interrupts.
249 * interrupts that begin execution with MSR[HV]=1 (so both MSR[HV] 0->1 and
250 * MSR[HV] 1->1).
256 * +-----------+------------+-------------+---------+-------------+-----+
262 * +--------------------------------------------------------------------+
268 CPUPPCState *env = &cpu->env; in ppc_excp_apply_ail()
280 if (!(pcc->lpcr_mask & LPCR_AIL)) { in ppc_excp_apply_ail()
286 if (!(pcc->lpcr_mask & LPCR_HAIL)) { in ppc_excp_apply_ail()
291 if (hv_escalation && !(env->spr[SPR_LPCR] & LPCR_HR)) { in ppc_excp_apply_ail()
293 * AIL does not work if there is a MSR[HV] 0->1 transition and the in ppc_excp_apply_ail()
300 ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; in ppc_excp_apply_ail()
311 * Guest->guest and HV->HV interrupts do require MMU on. in ppc_excp_apply_ail()
317 if (!(env->spr[SPR_LPCR] & LPCR_HAIL)) { in ppc_excp_apply_ail()
323 ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; in ppc_excp_apply_ail()
349 *vector &= ~0x0000000000017000ull; /* Un-apply the base offset */ in ppc_excp_apply_ail()
359 CPUPPCState *env = &cpu->env; in powerpc_reset_excp_state()
362 cs->exception_index = POWERPC_EXCP_NONE; in powerpc_reset_excp_state()
363 env->error_code = 0; in powerpc_reset_excp_state()
369 CPUPPCState *env = &cpu->env; in powerpc_set_excp_state()
371 assert((msr & env->msr_mask) == msr); in powerpc_set_excp_state()
377 * Note: We *MUST* not use hreg_store_msr() as-is anyway because it will in powerpc_set_excp_state()
380 env->nip = vector; in powerpc_set_excp_state()
381 env->msr = msr; in powerpc_set_excp_state()
394 env->reserve_addr = -1; in powerpc_set_excp_state()
400 if (FIELD_EX64(env->msr, MSR, ME)) { in powerpc_mcheck_checkstop()
409 CPUPPCState *env = &cpu->env; in powerpc_excp_40x()
413 /* new srr1 value excluding must-be-zero bits */ in powerpc_excp_40x()
414 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_40x()
417 new_msr = env->msr & (((target_ulong)1 << MSR_ME)); in powerpc_excp_40x()
424 vector = env->excp_vectors[excp]; in powerpc_excp_40x()
425 if (vector == (target_ulong)-1ULL) { in powerpc_excp_40x()
429 vector |= env->excp_prefix; in powerpc_excp_40x()
444 trace_ppc_excp_dsi(env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); in powerpc_excp_40x()
447 trace_ppc_excp_isi(msr, env->nip); in powerpc_excp_40x()
454 switch (env->error_code & ~0xF) { in powerpc_excp_40x()
456 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_40x()
461 env->spr[SPR_40x_ESR] = ESR_FP; in powerpc_excp_40x()
464 trace_ppc_excp_inval(env->nip); in powerpc_excp_40x()
465 env->spr[SPR_40x_ESR] = ESR_PIL; in powerpc_excp_40x()
468 env->spr[SPR_40x_ESR] = ESR_PPR; in powerpc_excp_40x()
471 env->spr[SPR_40x_ESR] = ESR_PTR; in powerpc_excp_40x()
475 env->error_code); in powerpc_excp_40x()
486 env->nip += 4; in powerpc_excp_40x()
488 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ in powerpc_excp_40x()
510 env->spr[srr0] = env->nip; in powerpc_excp_40x()
511 env->spr[srr1] = msr; in powerpc_excp_40x()
517 CPUPPCState *env = &cpu->env; in powerpc_excp_6xx()
520 /* new srr1 value excluding must-be-zero bits */ in powerpc_excp_6xx()
521 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_6xx()
524 new_msr = env->msr & ((target_ulong)1 << MSR_ME); in powerpc_excp_6xx()
531 vector = env->excp_vectors[excp]; in powerpc_excp_6xx()
532 if (vector == (target_ulong)-1ULL) { in powerpc_excp_6xx()
536 vector |= env->excp_prefix; in powerpc_excp_6xx()
547 trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); in powerpc_excp_6xx()
550 trace_ppc_excp_isi(msr, env->nip); in powerpc_excp_6xx()
551 msr |= env->error_code; in powerpc_excp_6xx()
562 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; in powerpc_excp_6xx()
565 switch (env->error_code & ~0xF) { in powerpc_excp_6xx()
567 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_6xx()
579 trace_ppc_excp_inval(env->nip); in powerpc_excp_6xx()
591 env->error_code); in powerpc_excp_6xx()
602 env->nip += 4; in powerpc_excp_6xx()
604 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ in powerpc_excp_6xx()
611 if (FIELD_EX64(env->msr, MSR, POW)) { in powerpc_excp_6xx()
613 "Trying to deliver power-saving system reset exception " in powerpc_excp_6xx()
630 msr |= env->crf[0] << 28; in powerpc_excp_6xx()
631 msr |= env->error_code; /* key, D/I, S/L bits */ in powerpc_excp_6xx()
633 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; in powerpc_excp_6xx()
635 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ in powerpc_excp_6xx()
653 env->spr[SPR_SRR0] = env->nip; in powerpc_excp_6xx()
654 env->spr[SPR_SRR1] = msr; in powerpc_excp_6xx()
660 CPUPPCState *env = &cpu->env; in powerpc_excp_7xx()
663 /* new srr1 value excluding must-be-zero bits */ in powerpc_excp_7xx()
664 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_7xx()
667 new_msr = env->msr & ((target_ulong)1 << MSR_ME); in powerpc_excp_7xx()
674 vector = env->excp_vectors[excp]; in powerpc_excp_7xx()
675 if (vector == (target_ulong)-1ULL) { in powerpc_excp_7xx()
679 vector |= env->excp_prefix; in powerpc_excp_7xx()
688 trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); in powerpc_excp_7xx()
691 trace_ppc_excp_isi(msr, env->nip); in powerpc_excp_7xx()
692 msr |= env->error_code; in powerpc_excp_7xx()
703 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; in powerpc_excp_7xx()
706 switch (env->error_code & ~0xF) { in powerpc_excp_7xx()
708 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_7xx()
720 trace_ppc_excp_inval(env->nip); in powerpc_excp_7xx()
732 env->error_code); in powerpc_excp_7xx()
738 int lev = env->error_code; in powerpc_excp_7xx()
740 if (lev == 1 && cpu->vhyp) { in powerpc_excp_7xx()
750 env->nip += 4; in powerpc_excp_7xx()
758 if (lev == 1 && cpu->vhyp) { in powerpc_excp_7xx()
759 cpu->vhyp_class->hypercall(cpu->vhyp, cpu); in powerpc_excp_7xx()
766 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ in powerpc_excp_7xx()
770 if (FIELD_EX64(env->msr, MSR, POW)) { in powerpc_excp_7xx()
772 "Trying to deliver power-saving system reset exception " in powerpc_excp_7xx()
782 msr |= env->crf[0] << 28; in powerpc_excp_7xx()
783 msr |= env->error_code; /* key, D/I, S/L bits */ in powerpc_excp_7xx()
785 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; in powerpc_excp_7xx()
803 env->spr[SPR_SRR0] = env->nip; in powerpc_excp_7xx()
804 env->spr[SPR_SRR1] = msr; in powerpc_excp_7xx()
810 CPUPPCState *env = &cpu->env; in powerpc_excp_74xx()
813 /* new srr1 value excluding must-be-zero bits */ in powerpc_excp_74xx()
814 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_74xx()
817 new_msr = env->msr & ((target_ulong)1 << MSR_ME); in powerpc_excp_74xx()
824 vector = env->excp_vectors[excp]; in powerpc_excp_74xx()
825 if (vector == (target_ulong)-1ULL) { in powerpc_excp_74xx()
829 vector |= env->excp_prefix; in powerpc_excp_74xx()
838 trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); in powerpc_excp_74xx()
841 trace_ppc_excp_isi(msr, env->nip); in powerpc_excp_74xx()
842 msr |= env->error_code; in powerpc_excp_74xx()
853 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; in powerpc_excp_74xx()
856 switch (env->error_code & ~0xF) { in powerpc_excp_74xx()
858 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_74xx()
870 trace_ppc_excp_inval(env->nip); in powerpc_excp_74xx()
882 env->error_code); in powerpc_excp_74xx()
888 int lev = env->error_code; in powerpc_excp_74xx()
890 if (lev == 1 && cpu->vhyp) { in powerpc_excp_74xx()
900 env->nip += 4; in powerpc_excp_74xx()
908 if (lev == 1 && cpu->vhyp) { in powerpc_excp_74xx()
909 cpu->vhyp_class->hypercall(cpu->vhyp, cpu); in powerpc_excp_74xx()
916 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ in powerpc_excp_74xx()
920 if (FIELD_EX64(env->msr, MSR, POW)) { in powerpc_excp_74xx()
922 "Trying to deliver power-saving system reset " in powerpc_excp_74xx()
947 env->spr[SPR_SRR0] = env->nip; in powerpc_excp_74xx()
948 env->spr[SPR_SRR1] = msr; in powerpc_excp_74xx()
954 CPUPPCState *env = &cpu->env; in powerpc_excp_booke()
962 msr = env->msr; in powerpc_excp_booke()
965 new_msr = env->msr & ((target_ulong)1 << MSR_ME); in powerpc_excp_booke()
982 vector = env->excp_vectors[excp]; in powerpc_excp_booke()
983 if (vector == (target_ulong)-1ULL) { in powerpc_excp_booke()
987 vector |= env->excp_prefix; in powerpc_excp_booke()
1003 env->spr[SPR_BOOKE_CSRR0] = env->nip; in powerpc_excp_booke()
1004 env->spr[SPR_BOOKE_CSRR1] = msr; in powerpc_excp_booke()
1008 trace_ppc_excp_dsi(env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); in powerpc_excp_booke()
1011 trace_ppc_excp_isi(msr, env->nip); in powerpc_excp_booke()
1014 if (env->mpic_proxy) { in powerpc_excp_booke()
1017 env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack); in powerpc_excp_booke()
1023 switch (env->error_code & ~0xF) { in powerpc_excp_booke()
1025 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_booke()
1035 env->spr[SPR_BOOKE_ESR] = ESR_FP; in powerpc_excp_booke()
1038 trace_ppc_excp_inval(env->nip); in powerpc_excp_booke()
1040 env->spr[SPR_BOOKE_ESR] = ESR_PIL; in powerpc_excp_booke()
1044 env->spr[SPR_BOOKE_ESR] = ESR_PPR; in powerpc_excp_booke()
1048 env->spr[SPR_BOOKE_ESR] = ESR_PTR; in powerpc_excp_booke()
1053 env->error_code); in powerpc_excp_booke()
1064 env->nip += 4; in powerpc_excp_booke()
1066 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ in powerpc_excp_booke()
1070 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ in powerpc_excp_booke()
1083 if (env->flags & POWERPC_FLAG_DE) { in powerpc_excp_booke()
1088 env->spr[SPR_BOOKE_CSRR0] = env->nip; in powerpc_excp_booke()
1089 env->spr[SPR_BOOKE_CSRR1] = msr; in powerpc_excp_booke()
1097 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */ in powerpc_excp_booke()
1098 env->spr[SPR_BOOKE_ESR] = ESR_SPV; in powerpc_excp_booke()
1107 if (FIELD_EX64(env->msr, MSR, POW)) { in powerpc_excp_booke()
1109 "Trying to deliver power-saving system reset " in powerpc_excp_booke()
1113 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ in powerpc_excp_booke()
1114 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ in powerpc_excp_booke()
1125 if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { in powerpc_excp_booke()
1126 /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ in powerpc_excp_booke()
1133 env->spr[srr0] = env->nip; in powerpc_excp_booke()
1134 env->spr[srr1] = msr; in powerpc_excp_booke()
1144 if (cpu->vhyp) { in books_vhyp_promotes_external_to_hvirt()
1153 * vhc->hypercall handler.
1157 if (cpu->vhyp) { in books_vhyp_handles_hcall()
1171 if (cpu->vhyp) { in books_vhyp_handles_hv_excp()
1180 if (!(env->insns_flags2 & PPC2_ISA310)) { in is_prefix_insn()
1188 CPUPPCState *env = &cpu->env; in is_prefix_insn_excp()
1190 if (!(env->insns_flags2 & PPC2_ISA310)) { in is_prefix_insn_excp()
1205 if (!(env->error_code & PPC_BIT(42))) { in is_prefix_insn_excp()
1215 if ((env->spr[SPR_HDSISR] & DSISR_PRTABLE_FAULT) && in is_prefix_insn_excp()
1216 (env->error_code == MMU_INST_FETCH)) { in is_prefix_insn_excp()
1243 return is_prefix_insn(env, ppc_ldl_code(env, env->nip)); in is_prefix_insn_excp()
1254 CPUPPCState *env = &cpu->env; in powerpc_excp_books()
1256 int srr0 = SPR_SRR0, srr1 = SPR_SRR1, lev = -1; in powerpc_excp_books()
1258 /* new srr1 value excluding must-be-zero bits */ in powerpc_excp_books()
1259 msr = env->msr & ~0x783f0000ULL; in powerpc_excp_books()
1265 new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); in powerpc_excp_books()
1271 if (env->resume_as_sreset) { in powerpc_excp_books()
1278 * unless running a nested-hv guest, in which case the L1 in powerpc_excp_books()
1281 if (excp == POWERPC_EXCP_HV_EMU && !(env->msr_mask & MSR_HVB) && in powerpc_excp_books()
1286 vector = env->excp_vectors[excp]; in powerpc_excp_books()
1287 if (vector == (target_ulong)-1ULL) { in powerpc_excp_books()
1291 vector |= env->excp_prefix; in powerpc_excp_books()
1300 if (env->msr_mask & MSR_HVB) { in powerpc_excp_books()
1311 msr |= env->error_code; in powerpc_excp_books()
1315 trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); in powerpc_excp_books()
1318 trace_ppc_excp_isi(msr, env->nip); in powerpc_excp_books()
1319 msr |= env->error_code; in powerpc_excp_books()
1326 if (!env->has_hv_mode) { in powerpc_excp_books()
1329 lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); in powerpc_excp_books()
1332 new_msr |= env->msr & ((target_ulong)1 << MSR_RI); in powerpc_excp_books()
1340 if (!(env->insns_flags2 & PPC2_ISA300)) { in powerpc_excp_books()
1347 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; in powerpc_excp_books()
1351 switch (env->error_code & ~0xF) { in powerpc_excp_books()
1353 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_books()
1365 trace_ppc_excp_inval(env->nip); in powerpc_excp_books()
1377 env->error_code); in powerpc_excp_books()
1382 lev = env->error_code; in powerpc_excp_books()
1384 if (lev == 1 && cpu->vhyp) { in powerpc_excp_books()
1394 env->nip += 4; in powerpc_excp_books()
1396 /* "PAPR mode" built-in hypercall emulation */ in powerpc_excp_books()
1398 cpu->vhyp_class->hypercall(cpu->vhyp, cpu); in powerpc_excp_books()
1402 if (env->insns_flags2 & PPC2_ISA310) { in powerpc_excp_books()
1411 lev = env->error_code; in powerpc_excp_books()
1413 env->nip += 4; in powerpc_excp_books()
1414 new_msr |= env->msr & ((target_ulong)1 << MSR_EE); in powerpc_excp_books()
1415 new_msr |= env->msr & ((target_ulong)1 << MSR_RI); in powerpc_excp_books()
1419 env->lr = env->nip; in powerpc_excp_books()
1420 env->ctr = msr; in powerpc_excp_books()
1422 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ in powerpc_excp_books()
1426 /* A power-saving exception sets ME, otherwise it is unchanged */ in powerpc_excp_books()
1427 if (FIELD_EX64(env->msr, MSR, POW)) { in powerpc_excp_books()
1432 if (env->msr_mask & MSR_HVB) { in powerpc_excp_books()
1439 if (FIELD_EX64(env->msr, MSR, POW)) { in powerpc_excp_books()
1441 "Trying to deliver power-saving system reset " in powerpc_excp_books()
1447 msr |= env->error_code; in powerpc_excp_books()
1455 msr |= env->error_code; in powerpc_excp_books()
1464 new_msr |= env->msr & ((target_ulong)1 << MSR_RI); in powerpc_excp_books()
1468 uint32_t insn = ppc_ldl_code(env, env->nip); in powerpc_excp_books()
1469 env->spr[SPR_HEIR] = insn; in powerpc_excp_books()
1471 uint32_t insn2 = ppc_ldl_code(env, env->nip + 4); in powerpc_excp_books()
1472 env->spr[SPR_HEIR] <<= 32; in powerpc_excp_books()
1473 env->spr[SPR_HEIR] |= insn2; in powerpc_excp_books()
1478 new_msr |= env->msr & ((target_ulong)1 << MSR_RI); in powerpc_excp_books()
1485 env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56); in powerpc_excp_books()
1488 env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS); in powerpc_excp_books()
1492 new_msr |= env->msr & ((target_ulong)1 << MSR_RI); in powerpc_excp_books()
1496 env->spr[SPR_BESCR] &= ~BESCR_GE; in powerpc_excp_books()
1502 env->spr[SPR_EBBRR] = env->nip; in powerpc_excp_books()
1503 powerpc_set_excp_state(cpu, env->spr[SPR_EBBHR], env->msr); in powerpc_excp_books()
1528 env->spr[srr0] = env->nip; in powerpc_excp_books()
1529 env->spr[srr1] = msr; in powerpc_excp_books()
1534 cpu->vhyp_class->deliver_hv_excp(cpu, excp); in powerpc_excp_books()
1538 if (!(env->msr_mask & MSR_HVB) && srr0 == SPR_HSRR0) { in powerpc_excp_books()
1556 CPUPPCState *env = &cpu->env; in powerpc_excp()
1564 " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp), in powerpc_excp()
1565 excp, env->error_code); in powerpc_excp()
1566 env->excp_stats[excp]++; in powerpc_excp()
1568 switch (env->excp_model) { in powerpc_excp()
1601 powerpc_excp(cpu, cs->exception_index); in ppc_cpu_do_interrupt()
1643 bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; in p7_next_unmasked_interrupt()
1647 if (cs->halted) { in p7_next_unmasked_interrupt()
1648 /* LPCR[PECE] controls which interrupts can exit power-saving mode */ in p7_next_unmasked_interrupt()
1660 bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); in p7_next_unmasked_interrupt()
1661 if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) { in p7_next_unmasked_interrupt()
1672 if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) && in p7_next_unmasked_interrupt()
1673 !FIELD_EX64(env->msr, MSR, PR))) || in p7_next_unmasked_interrupt()
1674 (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { in p7_next_unmasked_interrupt()
1736 bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; in p8_next_unmasked_interrupt()
1738 assert((env->pending_interrupts & P8_UNUSED_INTERRUPTS) == 0); in p8_next_unmasked_interrupt()
1740 if (cs->halted) { in p8_next_unmasked_interrupt()
1741 /* LPCR[PECE] controls which interrupts can exit power-saving mode */ in p8_next_unmasked_interrupt()
1754 if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) { in p8_next_unmasked_interrupt()
1765 if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) && in p8_next_unmasked_interrupt()
1766 !FIELD_EX64(env->msr, MSR, PR))) || in p8_next_unmasked_interrupt()
1767 (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { in p8_next_unmasked_interrupt()
1791 if (FIELD_EX64(env->msr, MSR, PR) && in p8_next_unmasked_interrupt()
1792 (env->spr[SPR_BESCR] & BESCR_GE)) { in p8_next_unmasked_interrupt()
1815 if (!heic || !FIELD_EX64_HV(env->msr) || in p9_interrupt_powersave()
1816 FIELD_EX64(env->msr, MSR, PR)) { in p9_interrupt_powersave()
1862 bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; in p9_next_unmasked_interrupt()
1866 if (cs->halted) { in p9_next_unmasked_interrupt()
1867 if (env->spr[SPR_PSSCR] & PSSCR_EC) { in p9_next_unmasked_interrupt()
1875 * When it's clear, any system-caused exception exits power-saving in p9_next_unmasked_interrupt()
1891 if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) { in p9_next_unmasked_interrupt()
1901 if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hvice) { in p9_next_unmasked_interrupt()
1911 if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) && in p9_next_unmasked_interrupt()
1912 !FIELD_EX64(env->msr, MSR, PR))) || in p9_next_unmasked_interrupt()
1913 (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { in p9_next_unmasked_interrupt()
1937 if (FIELD_EX64(env->msr, MSR, PR) && in p9_next_unmasked_interrupt()
1938 (env->spr[SPR_BESCR] & BESCR_GE)) { in p9_next_unmasked_interrupt()
1950 uint32_t pending_interrupts = env->pending_interrupts; in ppc_next_unmasked_interrupt()
1951 target_ulong lpcr = env->spr[SPR_LPCR]; in ppc_next_unmasked_interrupt()
1954 if (unlikely(env->quiesced)) { in ppc_next_unmasked_interrupt()
1959 switch (env->excp_model) { in ppc_next_unmasked_interrupt()
1983 if (env->pending_interrupts & PPC_INTERRUPT_DEBUG) { in ppc_next_unmasked_interrupt()
1994 async_deliver = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; in ppc_next_unmasked_interrupt()
2000 if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) { in ppc_next_unmasked_interrupt()
2010 if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) { in ppc_next_unmasked_interrupt()
2020 if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) && in ppc_next_unmasked_interrupt()
2021 !FIELD_EX64(env->msr, MSR, PR))) || in ppc_next_unmasked_interrupt()
2022 (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { in ppc_next_unmasked_interrupt()
2026 if (FIELD_EX64(env->msr, MSR, CE)) { in ppc_next_unmasked_interrupt()
2071 if (FIELD_EX64(env->msr, MSR, PR) && in ppc_next_unmasked_interrupt()
2072 (env->spr[SPR_BESCR] & BESCR_GE)) { in ppc_next_unmasked_interrupt()
2088 * - When relevant bits of MSR are altered, like EE, HV, PR, etc.;
2089 * - When relevant bits of LPCR are altered, like PECE, HDICE, HVICE, etc.;
2090 * - When PSSCR[EC] or env->resume_as_sreset are changed;
2091 * - When cs->halted is changed and the CPU has a different interrupt masking
2092 * logic in power-saving mode (e.g., POWER7/8/9/10);
2113 env->pending_interrupts &= ~PPC_INTERRUPT_MCK; in p7_deliver_interrupt()
2119 env->pending_interrupts &= ~PPC_INTERRUPT_HDECR; in p7_deliver_interrupt()
2149 assert(!env->resume_as_sreset); in p7_deliver_interrupt()
2163 env->pending_interrupts &= ~PPC_INTERRUPT_MCK; in p8_deliver_interrupt()
2169 env->pending_interrupts &= ~PPC_INTERRUPT_HDECR; in p8_deliver_interrupt()
2185 if (!env->resume_as_sreset) { in p8_deliver_interrupt()
2186 env->pending_interrupts &= ~PPC_INTERRUPT_DOORBELL; in p8_deliver_interrupt()
2195 if (!env->resume_as_sreset) { in p8_deliver_interrupt()
2196 env->pending_interrupts &= ~PPC_INTERRUPT_HDOORBELL; in p8_deliver_interrupt()
2204 env->pending_interrupts &= ~PPC_INTERRUPT_EBB; in p8_deliver_interrupt()
2205 if (env->spr[SPR_BESCR] & BESCR_PMEO) { in p8_deliver_interrupt()
2207 } else if (env->spr[SPR_BESCR] & BESCR_EEO) { in p8_deliver_interrupt()
2223 assert(!env->resume_as_sreset); in p8_deliver_interrupt()
2236 if (cs->halted && !(env->spr[SPR_PSSCR] & PSSCR_EC) && in p9_deliver_interrupt()
2237 !FIELD_EX64(env->msr, MSR, EE)) { in p9_deliver_interrupt()
2239 * A pending interrupt took us out of power-saving, but MSR[EE] says in p9_deliver_interrupt()
2247 env->pending_interrupts &= ~PPC_INTERRUPT_MCK; in p9_deliver_interrupt()
2254 env->pending_interrupts &= ~PPC_INTERRUPT_HDECR; in p9_deliver_interrupt()
2273 if (!env->resume_as_sreset) { in p9_deliver_interrupt()
2274 env->pending_interrupts &= ~PPC_INTERRUPT_DOORBELL; in p9_deliver_interrupt()
2279 if (!env->resume_as_sreset) { in p9_deliver_interrupt()
2280 env->pending_interrupts &= ~PPC_INTERRUPT_HDOORBELL; in p9_deliver_interrupt()
2288 env->pending_interrupts &= ~PPC_INTERRUPT_EBB; in p9_deliver_interrupt()
2289 if (env->spr[SPR_BESCR] & BESCR_PMEO) { in p9_deliver_interrupt()
2291 } else if (env->spr[SPR_BESCR] & BESCR_EEO) { in p9_deliver_interrupt()
2307 assert(!env->resume_as_sreset); in p9_deliver_interrupt()
2319 switch (env->excp_model) { in ppc_deliver_interrupt()
2336 env->pending_interrupts &= ~PPC_INTERRUPT_RESET; in ppc_deliver_interrupt()
2340 env->pending_interrupts &= ~PPC_INTERRUPT_MCK; in ppc_deliver_interrupt()
2346 env->pending_interrupts &= ~PPC_INTERRUPT_HDECR; in ppc_deliver_interrupt()
2365 env->pending_interrupts &= ~PPC_INTERRUPT_WDT; in ppc_deliver_interrupt()
2369 env->pending_interrupts &= ~PPC_INTERRUPT_CDOORBELL; in ppc_deliver_interrupt()
2373 env->pending_interrupts &= ~PPC_INTERRUPT_FIT; in ppc_deliver_interrupt()
2377 env->pending_interrupts &= ~PPC_INTERRUPT_PIT; in ppc_deliver_interrupt()
2382 env->pending_interrupts &= ~PPC_INTERRUPT_DECR; in ppc_deliver_interrupt()
2387 env->pending_interrupts &= ~PPC_INTERRUPT_DOORBELL; in ppc_deliver_interrupt()
2395 env->pending_interrupts &= ~PPC_INTERRUPT_HDOORBELL; in ppc_deliver_interrupt()
2402 env->pending_interrupts &= ~PPC_INTERRUPT_THERM; in ppc_deliver_interrupt()
2406 env->pending_interrupts &= ~PPC_INTERRUPT_EBB; in ppc_deliver_interrupt()
2407 if (env->spr[SPR_BESCR] & BESCR_PMEO) { in ppc_deliver_interrupt()
2409 } else if (env->spr[SPR_BESCR] & BESCR_EEO) { in ppc_deliver_interrupt()
2425 assert(!env->resume_as_sreset); in ppc_deliver_interrupt()
2442 cs->halted = 0; in ppc_cpu_do_system_reset()
2449 CPUPPCState *env = &cpu->env; in ppc_cpu_do_fwnmi_machine_check()
2457 msr |= env->msr & (1ULL << MSR_SF); in ppc_cpu_do_fwnmi_machine_check()
2464 cs->halted = 0; in ppc_cpu_do_fwnmi_machine_check()
2483 if (env->pending_interrupts == 0) { in ppc_cpu_exec_interrupt()