7  *  Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
11  * This library is free software; you can redistribute it and/or
75     /* Jump and branches */
88     /* Load and stores */
150     /* Cache and prefetch */
161     /* Instructions determined by bits 19 and 20 */
265  * R6 Multiply and Divide instructions have the same opcode
266  * and function field as legacy OPC_MULT[U]/OPC_DIV[U]
382     /* MIPS DSP Accumulator and DSPControl Access Sub-class */
675     /* MIPS DSP Accumulator and DSPControl Access Sub-class */
800     /* MIPS DSP Accumulator and DSPControl Access Sub-class */
1105  *         DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt
1172  * and the upper halves in cpu_gpr_hi[].
1493  * This is associated with the nabla symbol in the MIPS32 and MIPS64
1516  * if bit 0 of any register specification is set and the FR bit in the
1519  * in the Status register equals one, both even and odd register numbers
1682  * available, and, if that is not the case, generates a "reserved instruction"
1711  * Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL,
1712  * Config2 TL, and Config5 L2C are unset.
1740  * calling interface for 32 and 64-bit FPRs.  No sense in changing
2246 /* Load and store */
2599              * operands of different sign, first operand and the result  in gen_arith()
2667              * Operands of different sign, first operand and result different  in gen_arith()
2991         case R6_OPC_LDPC: /* bits 16 and 17 are part of immediate */  in gen_pcrel()
3403  * These MULT[U] and MADD[U] instructions implemented in for example
3404  * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
3413  * and
3422  * GPR rd and the special register LO. The high-order 32-bits of the
3820              * we can treat SRA and DSRA the same.  in gen_loongson_multimedia()
4469             /* Always take and link */  in gen_compute_branch()
4832 /* CP0 (MMU and control) */
11005     /* Load needed operands and calculate btarget */  in gen_compute_compact_branch()
13014              * Major opcode and function field is shared with preR6 MFHI/MTHI.  in decode_opc_special_r6()
13038              * Major opcode and function field is shared with preR6 MFHI/MTHI.  in decode_opc_special_r6()
13410     case OPC_MADD: /* Multiply and add/sub */  in decode_opc_special2_legacy()
13468             /* hint codes 24-31 are reserved and signal RI */  in decode_opc_special3_r6()
13579          * the same mask and op1.  in decode_opc_special3_legacy()
14122  * that is required, trapped and emulated by the Linux kernel. However, all
14125  * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
14126  * between SQ and RDHWR, as the Linux kernel does.
14166      * EVA loads and stores overlap Loongson 2E instructions decoded by  in decode_opc_special3()
14629     case OPC_LL: /* Load and stores */  in decode_opc_legacy()
14824     /* Compact branches [R6] and COP2 [non-R6] */  in decode_opc_legacy()
15109      * Execute a branch and its delay slot as a single instruction.  in mips_tr_init_disas_context()
15110      * This is what GDB expects and is consistent with what the  in mips_tr_init_disas_context()