Lines Matching full:env
38 CPUMIPSState *env = &c->env; in mips_vpe_is_wfi() local
44 return cpu->halted && mips_vpe_active(env); in mips_vpe_is_wfi()
50 CPUMIPSState *env = &c->env; in mips_vp_is_wfi() local
52 return cpu->halted && mips_vp_active(env); in mips_vp_is_wfi()
81 CPUMIPSState *c = &cpu->env; in mips_tc_wake()
91 CPUMIPSState *c = &cpu->env; in mips_tc_sleep()
101 * @env: CPU from which mapping is performed.
113 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) in mips_cpu_map_tc() argument
121 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { in mips_cpu_map_tc()
123 *tc = env->current_tc; in mips_cpu_map_tc()
124 return env; in mips_cpu_map_tc()
127 cs = env_cpu(env); in mips_cpu_map_tc()
132 return env; in mips_cpu_map_tc()
135 return &cpu->env; in mips_cpu_map_tc()
150 * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
205 uint32_t cpu_mips_get_random(CPUMIPSState *env) in cpu_mips_get_random() argument
210 uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired; in cpu_mips_get_random()
213 return env->tlb->nb_tlb - 1; in cpu_mips_get_random()
223 idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired; in cpu_mips_get_random()
230 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) in helper_mfc0_mvpcontrol() argument
232 return env->mvp->CP0_MVPControl; in helper_mfc0_mvpcontrol()
235 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env) in helper_mfc0_mvpconf0() argument
237 return env->mvp->CP0_MVPConf0; in helper_mfc0_mvpconf0()
240 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env) in helper_mfc0_mvpconf1() argument
242 return env->mvp->CP0_MVPConf1; in helper_mfc0_mvpconf1()
245 target_ulong helper_mfc0_random(CPUMIPSState *env) in helper_mfc0_random() argument
247 return (int32_t)cpu_mips_get_random(env); in helper_mfc0_random()
250 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env) in helper_mfc0_tcstatus() argument
252 return env->active_tc.CP0_TCStatus; in helper_mfc0_tcstatus()
255 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) in helper_mftc0_tcstatus() argument
257 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcstatus()
258 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tcstatus()
267 target_ulong helper_mfc0_tcbind(CPUMIPSState *env) in helper_mfc0_tcbind() argument
269 return env->active_tc.CP0_TCBind; in helper_mfc0_tcbind()
272 target_ulong helper_mftc0_tcbind(CPUMIPSState *env) in helper_mftc0_tcbind() argument
274 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcbind()
275 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tcbind()
284 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) in helper_mfc0_tcrestart() argument
286 return env->active_tc.PC; in helper_mfc0_tcrestart()
289 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) in helper_mftc0_tcrestart() argument
291 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcrestart()
292 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tcrestart()
301 target_ulong helper_mfc0_tchalt(CPUMIPSState *env) in helper_mfc0_tchalt() argument
303 return env->active_tc.CP0_TCHalt; in helper_mfc0_tchalt()
306 target_ulong helper_mftc0_tchalt(CPUMIPSState *env) in helper_mftc0_tchalt() argument
308 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tchalt()
309 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tchalt()
318 target_ulong helper_mfc0_tccontext(CPUMIPSState *env) in helper_mfc0_tccontext() argument
320 return env->active_tc.CP0_TCContext; in helper_mfc0_tccontext()
323 target_ulong helper_mftc0_tccontext(CPUMIPSState *env) in helper_mftc0_tccontext() argument
325 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tccontext()
326 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tccontext()
335 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) in helper_mfc0_tcschedule() argument
337 return env->active_tc.CP0_TCSchedule; in helper_mfc0_tcschedule()
340 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env) in helper_mftc0_tcschedule() argument
342 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcschedule()
343 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tcschedule()
352 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) in helper_mfc0_tcschefback() argument
354 return env->active_tc.CP0_TCScheFBack; in helper_mfc0_tcschefback()
357 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env) in helper_mftc0_tcschefback() argument
359 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcschefback()
360 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_tcschefback()
369 target_ulong helper_mfc0_count(CPUMIPSState *env) in helper_mfc0_count() argument
371 return (int32_t)cpu_mips_get_count(env); in helper_mfc0_count()
374 target_ulong helper_mftc0_entryhi(CPUMIPSState *env) in helper_mftc0_entryhi() argument
376 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_entryhi()
377 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_entryhi()
382 target_ulong helper_mftc0_cause(CPUMIPSState *env) in helper_mftc0_cause() argument
384 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_cause()
385 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_cause()
390 target_ulong helper_mftc0_status(CPUMIPSState *env) in helper_mftc0_status() argument
392 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_status()
393 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_status()
398 target_ulong helper_mfc0_lladdr(CPUMIPSState *env) in helper_mfc0_lladdr() argument
400 return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift); in helper_mfc0_lladdr()
403 target_ulong helper_mfc0_maar(CPUMIPSState *env) in helper_mfc0_maar() argument
405 return (int32_t) env->CP0_MAAR[env->CP0_MAARI]; in helper_mfc0_maar()
408 target_ulong helper_mfhc0_maar(CPUMIPSState *env) in helper_mfhc0_maar() argument
410 return env->CP0_MAAR[env->CP0_MAARI] >> 32; in helper_mfhc0_maar()
413 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel) in helper_mfc0_watchlo() argument
415 return (int32_t)env->CP0_WatchLo[sel]; in helper_mfc0_watchlo()
418 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) in helper_mfc0_watchhi() argument
420 return (int32_t) env->CP0_WatchHi[sel]; in helper_mfc0_watchhi()
423 target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel) in helper_mfhc0_watchhi() argument
425 return env->CP0_WatchHi[sel] >> 32; in helper_mfhc0_watchhi()
428 target_ulong helper_mfc0_debug(CPUMIPSState *env) in helper_mfc0_debug() argument
430 target_ulong t0 = env->CP0_Debug; in helper_mfc0_debug()
431 if (env->hflags & MIPS_HFLAG_DM) { in helper_mfc0_debug()
438 target_ulong helper_mftc0_debug(CPUMIPSState *env) in helper_mftc0_debug() argument
440 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_debug()
442 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_debug()
456 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env) in helper_dmfc0_tcrestart() argument
458 return env->active_tc.PC; in helper_dmfc0_tcrestart()
461 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env) in helper_dmfc0_tchalt() argument
463 return env->active_tc.CP0_TCHalt; in helper_dmfc0_tchalt()
466 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env) in helper_dmfc0_tccontext() argument
468 return env->active_tc.CP0_TCContext; in helper_dmfc0_tccontext()
471 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env) in helper_dmfc0_tcschedule() argument
473 return env->active_tc.CP0_TCSchedule; in helper_dmfc0_tcschedule()
476 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env) in helper_dmfc0_tcschefback() argument
478 return env->active_tc.CP0_TCScheFBack; in helper_dmfc0_tcschefback()
481 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env) in helper_dmfc0_lladdr() argument
483 return env->CP0_LLAddr >> env->CP0_LLAddr_shift; in helper_dmfc0_lladdr()
486 target_ulong helper_dmfc0_maar(CPUMIPSState *env) in helper_dmfc0_maar() argument
488 return env->CP0_MAAR[env->CP0_MAARI]; in helper_dmfc0_maar()
491 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) in helper_dmfc0_watchlo() argument
493 return env->CP0_WatchLo[sel]; in helper_dmfc0_watchlo()
496 target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel) in helper_dmfc0_watchhi() argument
498 return env->CP0_WatchHi[sel]; in helper_dmfc0_watchhi()
503 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_index() argument
505 uint32_t index_p = env->CP0_Index & 0x80000000; in helper_mtc0_index()
507 if (tlb_index < env->tlb->nb_tlb) { in helper_mtc0_index()
508 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_index()
511 env->CP0_Index = index_p | tlb_index; in helper_mtc0_index()
515 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_mvpcontrol() argument
520 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { in helper_mtc0_mvpcontrol()
524 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { in helper_mtc0_mvpcontrol()
527 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); in helper_mtc0_mvpcontrol()
531 env->mvp->CP0_MVPControl = newval; in helper_mtc0_mvpcontrol()
534 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_vpecontrol() argument
541 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); in helper_mtc0_vpecontrol()
550 env->CP0_VPEControl = newval; in helper_mtc0_vpecontrol()
553 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_vpecontrol() argument
555 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_vpecontrol()
556 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_vpecontrol()
569 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env) in helper_mftc0_vpecontrol() argument
571 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_vpecontrol()
572 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_vpecontrol()
577 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env) in helper_mftc0_vpeconf0() argument
579 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_vpeconf0()
580 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_vpeconf0()
585 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_vpeconf0() argument
590 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { in helper_mtc0_vpeconf0()
591 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) { in helper_mtc0_vpeconf0()
596 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); in helper_mtc0_vpeconf0()
600 env->CP0_VPEConf0 = newval; in helper_mtc0_vpeconf0()
603 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_vpeconf0() argument
605 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_vpeconf0()
606 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_vpeconf0()
617 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_vpeconf1() argument
622 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) in helper_mtc0_vpeconf1()
625 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); in helper_mtc0_vpeconf1()
632 env->CP0_VPEConf1 = newval; in helper_mtc0_vpeconf1()
635 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_yqmask() argument
638 env->CP0_YQMask = 0x00000000; in helper_mtc0_yqmask()
641 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_vpeopt() argument
643 env->CP0_VPEOpt = arg1 & 0x0000ffff; in helper_mtc0_vpeopt()
646 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF) argument
648 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_entrylo0() argument
651 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); in helper_mtc0_entrylo0()
652 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env)) in helper_mtc0_entrylo0()
657 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6) argument
659 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1) in helper_dmtc0_entrylo0() argument
661 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32); in helper_dmtc0_entrylo0()
662 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; in helper_dmtc0_entrylo0()
666 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tcstatus() argument
668 uint32_t mask = env->CP0_TCStatus_rw_bitmask; in helper_mtc0_tcstatus()
671 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); in helper_mtc0_tcstatus()
673 env->active_tc.CP0_TCStatus = newval; in helper_mtc0_tcstatus()
674 sync_c0_tcstatus(env, env->current_tc, newval); in helper_mtc0_tcstatus()
677 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tcstatus() argument
679 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcstatus()
680 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tcstatus()
690 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tcbind() argument
695 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { in helper_mtc0_tcbind()
698 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); in helper_mtc0_tcbind()
699 env->active_tc.CP0_TCBind = newval; in helper_mtc0_tcbind()
702 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tcbind() argument
704 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcbind()
707 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tcbind()
721 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tcrestart() argument
723 env->active_tc.PC = arg1; in helper_mtc0_tcrestart()
724 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); in helper_mtc0_tcrestart()
725 env->CP0_LLAddr = 0; in helper_mtc0_tcrestart()
726 env->lladdr = 0; in helper_mtc0_tcrestart()
730 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tcrestart() argument
732 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcrestart()
733 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tcrestart()
750 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tchalt() argument
752 MIPSCPU *cpu = env_archcpu(env); in helper_mtc0_tchalt()
754 env->active_tc.CP0_TCHalt = arg1 & 0x1; in helper_mtc0_tchalt()
757 if (env->active_tc.CP0_TCHalt & 1) { in helper_mtc0_tchalt()
758 mips_tc_sleep(cpu, env->current_tc); in helper_mtc0_tchalt()
760 mips_tc_wake(cpu, env->current_tc); in helper_mtc0_tchalt()
764 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tchalt() argument
766 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tchalt()
767 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tchalt()
785 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tccontext() argument
787 env->active_tc.CP0_TCContext = arg1; in helper_mtc0_tccontext()
790 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tccontext() argument
792 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tccontext()
793 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tccontext()
802 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tcschedule() argument
804 env->active_tc.CP0_TCSchedule = arg1; in helper_mtc0_tcschedule()
807 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tcschedule() argument
809 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcschedule()
810 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tcschedule()
819 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_tcschefback() argument
821 env->active_tc.CP0_TCScheFBack = arg1; in helper_mtc0_tcschefback()
824 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_tcschefback() argument
826 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcschefback()
827 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_tcschefback()
836 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_entrylo1() argument
839 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); in helper_mtc0_entrylo1()
840 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env)) in helper_mtc0_entrylo1()
845 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1) in helper_dmtc0_entrylo1() argument
847 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32); in helper_dmtc0_entrylo1()
848 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; in helper_dmtc0_entrylo1()
852 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_context() argument
854 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); in helper_mtc0_context()
857 void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_memorymapid() argument
860 old = env->CP0_MemoryMapID; in helper_mtc0_memorymapid()
861 env->CP0_MemoryMapID = (int32_t) arg1; in helper_mtc0_memorymapid()
863 if (old != env->CP0_MemoryMapID) { in helper_mtc0_memorymapid()
864 cpu_mips_tlb_flush(env); in helper_mtc0_memorymapid()
883 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_pagemask() argument
885 env->CP0_PageMask = compute_pagemask(arg1); in helper_mtc0_pagemask()
888 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_pagegrain() argument
892 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) | in helper_mtc0_pagegrain()
893 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask); in helper_mtc0_pagegrain()
894 compute_hflags(env); in helper_mtc0_pagegrain()
895 restore_pamask(env); in helper_mtc0_pagegrain()
898 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_segctl0() argument
900 CPUState *cs = env_cpu(env); in helper_mtc0_segctl0()
902 env->CP0_SegCtl0 = arg1 & CP0SC0_MASK; in helper_mtc0_segctl0()
906 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_segctl1() argument
908 CPUState *cs = env_cpu(env); in helper_mtc0_segctl1()
910 env->CP0_SegCtl1 = arg1 & CP0SC1_MASK; in helper_mtc0_segctl1()
914 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_segctl2() argument
916 CPUState *cs = env_cpu(env); in helper_mtc0_segctl2()
918 env->CP0_SegCtl2 = arg1 & CP0SC2_MASK; in helper_mtc0_segctl2()
922 void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_pwfield() argument
926 uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL; in helper_mtc0_pwfield()
929 if ((env->insn_flags & ISA_MIPS_R6)) { in helper_mtc0_pwfield()
946 env->CP0_PWField = arg1 & mask; in helper_mtc0_pwfield()
949 ((env->insn_flags & ISA_MIPS_R6) && in helper_mtc0_pwfield()
951 env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) | in helper_mtc0_pwfield()
956 uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; in helper_mtc0_pwfield()
959 if ((env->insn_flags & ISA_MIPS_R6)) { in helper_mtc0_pwfield()
973 env->CP0_PWField = arg1 & mask; in helper_mtc0_pwfield()
976 ((env->insn_flags & ISA_MIPS_R6) && in helper_mtc0_pwfield()
978 env->CP0_PWField = (env->CP0_PWField & ~0x3F) | in helper_mtc0_pwfield()
984 void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_pwsize() argument
987 env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL; in helper_mtc0_pwsize()
989 env->CP0_PWSize = arg1 & 0x3FFFFFFF; in helper_mtc0_pwsize()
993 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_wired() argument
995 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_wired()
996 if (arg1 < env->tlb->nb_tlb) { in helper_mtc0_wired()
997 env->CP0_Wired = arg1; in helper_mtc0_wired()
1000 env->CP0_Wired = arg1 % env->tlb->nb_tlb; in helper_mtc0_wired()
1004 void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_pwctl() argument
1008 env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F); in helper_mtc0_pwctl()
1010 env->CP0_PWCtl = (arg1 & 0x800000FF); in helper_mtc0_pwctl()
1014 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_srsconf0() argument
1016 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; in helper_mtc0_srsconf0()
1019 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_srsconf1() argument
1021 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; in helper_mtc0_srsconf1()
1024 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_srsconf2() argument
1026 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; in helper_mtc0_srsconf2()
1029 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_srsconf3() argument
1031 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; in helper_mtc0_srsconf3()
1034 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_srsconf4() argument
1036 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; in helper_mtc0_srsconf4()
1039 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_hwrena() argument
1043 if ((env->CP0_Config1 & (1 << CP0C1_PC)) && in helper_mtc0_hwrena()
1044 (env->insn_flags & ISA_MIPS_R6)) { in helper_mtc0_hwrena()
1047 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_hwrena()
1050 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { in helper_mtc0_hwrena()
1054 env->hflags |= MIPS_HFLAG_HWRENA_ULR; in helper_mtc0_hwrena()
1056 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR; in helper_mtc0_hwrena()
1060 env->CP0_HWREna = arg1 & mask; in helper_mtc0_hwrena()
1063 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_count() argument
1065 cpu_mips_store_count(env, arg1); in helper_mtc0_count()
1068 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_entryhi() argument
1071 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask; in helper_mtc0_entryhi()
1072 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) { in helper_mtc0_entryhi()
1078 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_entryhi()
1080 int config0_at = extract32(env->CP0_Config0, 13, 2); in helper_mtc0_entryhi()
1081 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0; in helper_mtc0_entryhi()
1088 mask &= env->SEGMask; in helper_mtc0_entryhi()
1090 old = env->CP0_EntryHi; in helper_mtc0_entryhi()
1092 env->CP0_EntryHi = val; in helper_mtc0_entryhi()
1093 if (ase_mt_available(env)) { in helper_mtc0_entryhi()
1094 sync_c0_entryhi(env, env->current_tc); in helper_mtc0_entryhi()
1097 if ((old & env->CP0_EntryHi_ASID_mask) != in helper_mtc0_entryhi()
1098 (val & env->CP0_EntryHi_ASID_mask)) { in helper_mtc0_entryhi()
1099 tlb_flush(env_cpu(env)); in helper_mtc0_entryhi()
1103 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_entryhi() argument
1105 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_entryhi()
1106 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_entryhi()
1112 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_compare() argument
1114 cpu_mips_store_compare(env, arg1); in helper_mtc0_compare()
1117 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_status() argument
1121 old = env->CP0_Status; in helper_mtc0_status()
1122 cpu_mips_store_status(env, arg1); in helper_mtc0_status()
1123 val = env->CP0_Status; in helper_mtc0_status()
1127 old, old & env->CP0_Cause & CP0Ca_IP_mask, in helper_mtc0_status()
1128 val, val & env->CP0_Cause & CP0Ca_IP_mask, in helper_mtc0_status()
1129 env->CP0_Cause); in helper_mtc0_status()
1130 switch (mips_env_mmu_index(env)) { in helper_mtc0_status()
1144 cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); in helper_mtc0_status()
1150 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_status() argument
1152 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_status()
1153 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018; in helper_mttc0_status()
1154 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_status()
1157 sync_c0_status(env, other, other_tc); in helper_mttc0_status()
1160 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_intctl() argument
1162 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0); in helper_mtc0_intctl()
1165 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_srsctl() argument
1168 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); in helper_mtc0_srsctl()
1171 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_cause() argument
1173 cpu_mips_store_cause(env, arg1); in helper_mtc0_cause()
1176 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_cause() argument
1178 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_cause()
1179 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_cause()
1184 target_ulong helper_mftc0_epc(CPUMIPSState *env) in helper_mftc0_epc() argument
1186 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_epc()
1187 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_epc()
1192 target_ulong helper_mftc0_ebase(CPUMIPSState *env) in helper_mftc0_ebase() argument
1194 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_ebase()
1195 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_ebase()
1200 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_ebase() argument
1202 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; in helper_mtc0_ebase()
1203 if (arg1 & env->CP0_EBaseWG_rw_bitmask) { in helper_mtc0_ebase()
1206 env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask); in helper_mtc0_ebase()
1209 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_ebase() argument
1211 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_ebase()
1212 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_ebase()
1213 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; in helper_mttc0_ebase()
1214 if (arg1 & env->CP0_EBaseWG_rw_bitmask) { in helper_mttc0_ebase()
1220 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx) in helper_mftc0_configx() argument
1222 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_configx()
1223 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftc0_configx()
1239 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_config0() argument
1241 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); in helper_mtc0_config0()
1244 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_config2() argument
1247 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); in helper_mtc0_config2()
1250 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_config3() argument
1252 if (env->insn_flags & ASE_MICROMIPS) { in helper_mtc0_config3()
1253 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) | in helper_mtc0_config3()
1258 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_config4() argument
1260 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) | in helper_mtc0_config4()
1261 (arg1 & env->CP0_Config4_rw_bitmask); in helper_mtc0_config4()
1264 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_config5() argument
1266 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) | in helper_mtc0_config5()
1267 (arg1 & env->CP0_Config5_rw_bitmask); in helper_mtc0_config5()
1268 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in helper_mtc0_config5()
1269 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; in helper_mtc0_config5()
1270 compute_hflags(env); in helper_mtc0_config5()
1273 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_lladdr() argument
1275 target_long mask = env->CP0_LLAddr_rw_bitmask; in helper_mtc0_lladdr()
1276 arg1 = arg1 << env->CP0_LLAddr_shift; in helper_mtc0_lladdr()
1277 env->CP0_LLAddr = (env->CP0_LLAddr & ~mask) | (arg1 & mask); in helper_mtc0_lladdr()
1280 #define MTC0_MAAR_MASK(env) \ argument
1281 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1283 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_maar() argument
1285 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env); in helper_mtc0_maar()
1288 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1) in helper_mthc0_maar() argument
1290 env->CP0_MAAR[env->CP0_MAARI] = in helper_mthc0_maar()
1291 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) | in helper_mthc0_maar()
1292 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL); in helper_mthc0_maar()
1295 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_maari() argument
1303 env->CP0_MAARI = MIPS_MAAR_MAX - 1; in helper_mtc0_maari()
1305 env->CP0_MAARI = index; in helper_mtc0_maari()
1313 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mtc0_watchlo() argument
1319 env->CP0_WatchLo[sel] = (arg1 & ~0x7); in helper_mtc0_watchlo()
1322 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mtc0_watchhi() argument
1324 uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID); in helper_mtc0_watchhi()
1325 uint64_t m_bit = env->CP0_WatchHi[sel] & (1 << CP0WH_M); /* read-only */ in helper_mtc0_watchhi()
1326 if ((env->CP0_Config5 >> CP0C5_MI) & 1) { in helper_mtc0_watchhi()
1329 env->CP0_WatchHi[sel] = m_bit | (arg1 & mask); in helper_mtc0_watchhi()
1330 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); in helper_mtc0_watchhi()
1333 void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mthc0_watchhi() argument
1335 env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) | in helper_mthc0_watchhi()
1336 (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL); in helper_mthc0_watchhi()
1339 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_xcontext() argument
1341 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; in helper_mtc0_xcontext()
1342 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); in helper_mtc0_xcontext()
1345 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_framemask() argument
1347 env->CP0_Framemask = arg1; /* XXX */ in helper_mtc0_framemask()
1350 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_debug() argument
1352 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); in helper_mtc0_debug()
1354 env->hflags |= MIPS_HFLAG_DM; in helper_mtc0_debug()
1356 env->hflags &= ~MIPS_HFLAG_DM; in helper_mtc0_debug()
1360 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1) in helper_mttc0_debug() argument
1362 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_debug()
1364 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttc0_debug()
1377 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_performance0() argument
1379 env->CP0_Performance0 = arg1 & 0x000007ff; in helper_mtc0_performance0()
1382 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_errctl() argument
1386 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0; in helper_mtc0_errctl()
1388 env->CP0_ErrCtl = wst | spr | itc; in helper_mtc0_errctl()
1391 env->hflags |= MIPS_HFLAG_ITC_CACHE; in helper_mtc0_errctl()
1393 env->hflags &= ~MIPS_HFLAG_ITC_CACHE; in helper_mtc0_errctl()
1397 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_taglo() argument
1399 if (env->hflags & MIPS_HFLAG_ITC_CACHE) { in helper_mtc0_taglo()
1405 env->CP0_TagLo = arg1; in helper_mtc0_taglo()
1407 env->CP0_TagLo = arg1 & 0xFFFFFCF6; in helper_mtc0_taglo()
1411 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_datalo() argument
1413 env->CP0_DataLo = arg1; /* XXX */ in helper_mtc0_datalo()
1416 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_taghi() argument
1418 env->CP0_TagHi = arg1; /* XXX */ in helper_mtc0_taghi()
1421 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1) in helper_mtc0_datahi() argument
1423 env->CP0_DataHi = arg1; /* XXX */ in helper_mtc0_datahi()
1427 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel) in helper_mftgpr() argument
1429 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftgpr()
1430 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftgpr()
1439 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) in helper_mftlo() argument
1441 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftlo()
1442 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftlo()
1451 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) in helper_mfthi() argument
1453 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mfthi()
1454 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mfthi()
1463 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) in helper_mftacx() argument
1465 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftacx()
1466 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftacx()
1475 target_ulong helper_mftdsp(CPUMIPSState *env) in helper_mftdsp() argument
1477 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftdsp()
1478 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mftdsp()
1487 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mttgpr() argument
1489 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttgpr()
1490 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttgpr()
1499 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mttlo() argument
1501 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttlo()
1502 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttlo()
1511 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mtthi() argument
1513 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mtthi()
1514 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mtthi()
1523 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) in helper_mttacx() argument
1525 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttacx()
1526 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttacx()
1535 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1) in helper_mttdsp() argument
1537 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttdsp()
1538 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); in helper_mttdsp()
1560 target_ulong helper_dvpe(CPUMIPSState *env) in helper_dvpe() argument
1563 target_ulong prev = env->mvp->CP0_MVPControl; in helper_dvpe()
1568 if (&other_cpu->env != env) { in helper_dvpe()
1569 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); in helper_dvpe()
1576 target_ulong helper_evpe(CPUMIPSState *env) in helper_evpe() argument
1579 target_ulong prev = env->mvp->CP0_MVPControl; in helper_evpe()
1584 if (&other_cpu->env != env in helper_evpe()
1588 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); in helper_evpe()
1596 target_ulong helper_dvp(CPUMIPSState *env) in helper_dvp() argument
1599 target_ulong prev = env->CP0_VPControl; in helper_dvp()
1601 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) { in helper_dvp()
1605 if (&other_cpu->env != env) { in helper_dvp()
1609 env->CP0_VPControl |= (1 << CP0VPCtl_DIS); in helper_dvp()
1614 target_ulong helper_evp(CPUMIPSState *env) in helper_evp() argument
1617 target_ulong prev = env->CP0_VPControl; in helper_evp()
1619 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { in helper_evp()
1622 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) { in helper_evp()
1630 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS); in helper_evp()