Lines Matching +full:- +full:- +full:-
2 * Helpers for emulation of CP0-related MIPS instructions.
4 * Copyright (C) 2004-2005 Jocelyn Mayer
25 #include "qemu/main-loop.h"
28 #include "qemu/host-utils.h"
29 #include "exec/helper-proto.h"
38 CPUMIPSState *env = &c->env; in mips_vpe_is_wfi()
44 return cpu->halted && mips_vpe_active(env); in mips_vpe_is_wfi()
50 CPUMIPSState *env = &c->env; in mips_vp_is_wfi()
52 return cpu->halted && mips_vp_active(env); in mips_vp_is_wfi()
58 * Don't set ->halted = 0 directly, let it be done via cpu_has_work in mips_vpe_wake()
75 cs->halted = 1; in mips_vpe_sleep()
81 CPUMIPSState *c = &cpu->env; in mips_tc_wake()
91 CPUMIPSState *c = &cpu->env; in mips_tc_sleep()
121 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { in mips_cpu_map_tc()
123 *tc = env->current_tc; in mips_cpu_map_tc()
128 vpe_idx = tc_idx / cs->nr_threads; in mips_cpu_map_tc()
129 *tc = tc_idx % cs->nr_threads; in mips_cpu_map_tc()
135 return &cpu->env; in mips_cpu_map_tc()
169 tasid = v & cpu->CP0_EntryHi_ASID_mask; in sync_c0_tcstatus()
176 cpu->CP0_Status &= ~mask; in sync_c0_tcstatus()
177 cpu->CP0_Status |= status; in sync_c0_tcstatus()
180 cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask; in sync_c0_tcstatus()
181 cpu->CP0_EntryHi |= tasid; in sync_c0_tcstatus()
190 uint32_t asid, v = cpu->CP0_EntryHi; in sync_c0_entryhi()
192 asid = v & cpu->CP0_EntryHi_ASID_mask; in sync_c0_entryhi()
194 if (tc == cpu->current_tc) { in sync_c0_entryhi()
195 tcst = &cpu->active_tc.CP0_TCStatus; in sync_c0_entryhi()
197 tcst = &cpu->tcs[tc].CP0_TCStatus; in sync_c0_entryhi()
200 *tcst &= ~cpu->CP0_EntryHi_ASID_mask; in sync_c0_entryhi()
210 uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired; in cpu_mips_get_random()
213 return env->tlb->nb_tlb - 1; in cpu_mips_get_random()
223 idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired; in cpu_mips_get_random()
232 return env->mvp->CP0_MVPControl; in helper_mfc0_mvpcontrol()
237 return env->mvp->CP0_MVPConf0; in helper_mfc0_mvpconf0()
242 return env->mvp->CP0_MVPConf1; in helper_mfc0_mvpconf1()
252 return env->active_tc.CP0_TCStatus; in helper_mfc0_tcstatus()
257 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcstatus()
260 if (other_tc == other->current_tc) { in helper_mftc0_tcstatus()
261 return other->active_tc.CP0_TCStatus; in helper_mftc0_tcstatus()
263 return other->tcs[other_tc].CP0_TCStatus; in helper_mftc0_tcstatus()
269 return env->active_tc.CP0_TCBind; in helper_mfc0_tcbind()
274 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcbind()
277 if (other_tc == other->current_tc) { in helper_mftc0_tcbind()
278 return other->active_tc.CP0_TCBind; in helper_mftc0_tcbind()
280 return other->tcs[other_tc].CP0_TCBind; in helper_mftc0_tcbind()
286 return env->active_tc.PC; in helper_mfc0_tcrestart()
291 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcrestart()
294 if (other_tc == other->current_tc) { in helper_mftc0_tcrestart()
295 return other->active_tc.PC; in helper_mftc0_tcrestart()
297 return other->tcs[other_tc].PC; in helper_mftc0_tcrestart()
303 return env->active_tc.CP0_TCHalt; in helper_mfc0_tchalt()
308 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tchalt()
311 if (other_tc == other->current_tc) { in helper_mftc0_tchalt()
312 return other->active_tc.CP0_TCHalt; in helper_mftc0_tchalt()
314 return other->tcs[other_tc].CP0_TCHalt; in helper_mftc0_tchalt()
320 return env->active_tc.CP0_TCContext; in helper_mfc0_tccontext()
325 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tccontext()
328 if (other_tc == other->current_tc) { in helper_mftc0_tccontext()
329 return other->active_tc.CP0_TCContext; in helper_mftc0_tccontext()
331 return other->tcs[other_tc].CP0_TCContext; in helper_mftc0_tccontext()
337 return env->active_tc.CP0_TCSchedule; in helper_mfc0_tcschedule()
342 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcschedule()
345 if (other_tc == other->current_tc) { in helper_mftc0_tcschedule()
346 return other->active_tc.CP0_TCSchedule; in helper_mftc0_tcschedule()
348 return other->tcs[other_tc].CP0_TCSchedule; in helper_mftc0_tcschedule()
354 return env->active_tc.CP0_TCScheFBack; in helper_mfc0_tcschefback()
359 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_tcschefback()
362 if (other_tc == other->current_tc) { in helper_mftc0_tcschefback()
363 return other->active_tc.CP0_TCScheFBack; in helper_mftc0_tcschefback()
365 return other->tcs[other_tc].CP0_TCScheFBack; in helper_mftc0_tcschefback()
376 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_entryhi()
379 return other->CP0_EntryHi; in helper_mftc0_entryhi()
384 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_cause()
387 return other->CP0_Cause; in helper_mftc0_cause()
392 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_status()
395 return other->CP0_Status; in helper_mftc0_status()
400 return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift); in helper_mfc0_lladdr()
405 return (int32_t) env->CP0_MAAR[env->CP0_MAARI]; in helper_mfc0_maar()
410 return env->CP0_MAAR[env->CP0_MAARI] >> 32; in helper_mfhc0_maar()
415 return (int32_t)env->CP0_WatchLo[sel]; in helper_mfc0_watchlo()
420 return (int32_t) env->CP0_WatchHi[sel]; in helper_mfc0_watchhi()
425 return env->CP0_WatchHi[sel] >> 32; in helper_mfhc0_watchhi()
430 target_ulong t0 = env->CP0_Debug; in helper_mfc0_debug()
431 if (env->hflags & MIPS_HFLAG_DM) { in helper_mfc0_debug()
440 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_debug()
444 if (other_tc == other->current_tc) { in helper_mftc0_debug()
445 tcstatus = other->active_tc.CP0_Debug_tcstatus; in helper_mftc0_debug()
447 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus; in helper_mftc0_debug()
451 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | in helper_mftc0_debug()
458 return env->active_tc.PC; in helper_dmfc0_tcrestart()
463 return env->active_tc.CP0_TCHalt; in helper_dmfc0_tchalt()
468 return env->active_tc.CP0_TCContext; in helper_dmfc0_tccontext()
473 return env->active_tc.CP0_TCSchedule; in helper_dmfc0_tcschedule()
478 return env->active_tc.CP0_TCScheFBack; in helper_dmfc0_tcschefback()
483 return env->CP0_LLAddr >> env->CP0_LLAddr_shift; in helper_dmfc0_lladdr()
488 return env->CP0_MAAR[env->CP0_MAARI]; in helper_dmfc0_maar()
493 return env->CP0_WatchLo[sel]; in helper_dmfc0_watchlo()
498 return env->CP0_WatchHi[sel]; in helper_dmfc0_watchhi()
505 uint32_t index_p = env->CP0_Index & 0x80000000; in helper_mtc0_index()
507 if (tlb_index < env->tlb->nb_tlb) { in helper_mtc0_index()
508 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_index()
511 env->CP0_Index = index_p | tlb_index; in helper_mtc0_index()
520 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { in helper_mtc0_mvpcontrol()
524 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { in helper_mtc0_mvpcontrol()
527 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); in helper_mtc0_mvpcontrol()
531 env->mvp->CP0_MVPControl = newval; in helper_mtc0_mvpcontrol()
541 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); in helper_mtc0_vpecontrol()
550 env->CP0_VPEControl = newval; in helper_mtc0_vpecontrol()
555 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_vpecontrol()
562 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask); in helper_mttc0_vpecontrol()
566 other->CP0_VPEControl = newval; in helper_mttc0_vpecontrol()
571 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_vpecontrol()
574 return other->CP0_VPEControl; in helper_mftc0_vpecontrol()
579 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_vpeconf0()
582 return other->CP0_VPEConf0; in helper_mftc0_vpeconf0()
590 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { in helper_mtc0_vpeconf0()
591 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) { in helper_mtc0_vpeconf0()
596 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); in helper_mtc0_vpeconf0()
600 env->CP0_VPEConf0 = newval; in helper_mtc0_vpeconf0()
605 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_vpeconf0()
611 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask); in helper_mttc0_vpeconf0()
614 other->CP0_VPEConf0 = newval; in helper_mttc0_vpeconf0()
622 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) in helper_mtc0_vpeconf1()
625 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); in helper_mtc0_vpeconf1()
632 env->CP0_VPEConf1 = newval; in helper_mtc0_vpeconf1()
638 env->CP0_YQMask = 0x00000000; in helper_mtc0_yqmask()
643 env->CP0_VPEOpt = arg1 & 0x0000ffff; in helper_mtc0_vpeopt()
646 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
651 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); in helper_mtc0_entrylo0()
652 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env)) in helper_mtc0_entrylo0()
653 | (rxi << (CP0EnLo_XI - 30)); in helper_mtc0_entrylo0()
657 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
661 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32); in helper_dmtc0_entrylo0()
662 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; in helper_dmtc0_entrylo0()
668 uint32_t mask = env->CP0_TCStatus_rw_bitmask; in helper_mtc0_tcstatus()
671 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); in helper_mtc0_tcstatus()
673 env->active_tc.CP0_TCStatus = newval; in helper_mtc0_tcstatus()
674 sync_c0_tcstatus(env, env->current_tc, newval); in helper_mtc0_tcstatus()
679 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcstatus()
682 if (other_tc == other->current_tc) { in helper_mttc0_tcstatus()
683 other->active_tc.CP0_TCStatus = arg1; in helper_mttc0_tcstatus()
685 other->tcs[other_tc].CP0_TCStatus = arg1; in helper_mttc0_tcstatus()
695 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { in helper_mtc0_tcbind()
698 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); in helper_mtc0_tcbind()
699 env->active_tc.CP0_TCBind = newval; in helper_mtc0_tcbind()
704 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcbind()
709 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { in helper_mttc0_tcbind()
712 if (other_tc == other->current_tc) { in helper_mttc0_tcbind()
713 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); in helper_mttc0_tcbind()
714 other->active_tc.CP0_TCBind = newval; in helper_mttc0_tcbind()
716 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask); in helper_mttc0_tcbind()
717 other->tcs[other_tc].CP0_TCBind = newval; in helper_mttc0_tcbind()
723 env->active_tc.PC = arg1; in helper_mtc0_tcrestart()
724 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); in helper_mtc0_tcrestart()
725 env->CP0_LLAddr = 0; in helper_mtc0_tcrestart()
726 env->lladdr = 0; in helper_mtc0_tcrestart()
732 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcrestart()
735 if (other_tc == other->current_tc) { in helper_mttc0_tcrestart()
736 other->active_tc.PC = arg1; in helper_mttc0_tcrestart()
737 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); in helper_mttc0_tcrestart()
738 other->CP0_LLAddr = 0; in helper_mttc0_tcrestart()
739 other->lladdr = 0; in helper_mttc0_tcrestart()
742 other->tcs[other_tc].PC = arg1; in helper_mttc0_tcrestart()
743 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS); in helper_mttc0_tcrestart()
744 other->CP0_LLAddr = 0; in helper_mttc0_tcrestart()
745 other->lladdr = 0; in helper_mttc0_tcrestart()
754 env->active_tc.CP0_TCHalt = arg1 & 0x1; in helper_mtc0_tchalt()
757 if (env->active_tc.CP0_TCHalt & 1) { in helper_mtc0_tchalt()
758 mips_tc_sleep(cpu, env->current_tc); in helper_mtc0_tchalt()
760 mips_tc_wake(cpu, env->current_tc); in helper_mtc0_tchalt()
766 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tchalt()
772 if (other_tc == other->current_tc) { in helper_mttc0_tchalt()
773 other->active_tc.CP0_TCHalt = arg1; in helper_mttc0_tchalt()
775 other->tcs[other_tc].CP0_TCHalt = arg1; in helper_mttc0_tchalt()
787 env->active_tc.CP0_TCContext = arg1; in helper_mtc0_tccontext()
792 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tccontext()
795 if (other_tc == other->current_tc) { in helper_mttc0_tccontext()
796 other->active_tc.CP0_TCContext = arg1; in helper_mttc0_tccontext()
798 other->tcs[other_tc].CP0_TCContext = arg1; in helper_mttc0_tccontext()
804 env->active_tc.CP0_TCSchedule = arg1; in helper_mtc0_tcschedule()
809 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcschedule()
812 if (other_tc == other->current_tc) { in helper_mttc0_tcschedule()
813 other->active_tc.CP0_TCSchedule = arg1; in helper_mttc0_tcschedule()
815 other->tcs[other_tc].CP0_TCSchedule = arg1; in helper_mttc0_tcschedule()
821 env->active_tc.CP0_TCScheFBack = arg1; in helper_mtc0_tcschefback()
826 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_tcschefback()
829 if (other_tc == other->current_tc) { in helper_mttc0_tcschefback()
830 other->active_tc.CP0_TCScheFBack = arg1; in helper_mttc0_tcschefback()
832 other->tcs[other_tc].CP0_TCScheFBack = arg1; in helper_mttc0_tcschefback()
839 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); in helper_mtc0_entrylo1()
840 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env)) in helper_mtc0_entrylo1()
841 | (rxi << (CP0EnLo_XI - 30)); in helper_mtc0_entrylo1()
847 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32); in helper_dmtc0_entrylo1()
848 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; in helper_dmtc0_entrylo1()
854 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); in helper_mtc0_context()
860 old = env->CP0_MemoryMapID; in helper_mtc0_memorymapid()
861 env->CP0_MemoryMapID = (int32_t) arg1; in helper_mtc0_memorymapid()
863 if (old != env->CP0_MemoryMapID) { in helper_mtc0_memorymapid()
885 env->CP0_PageMask = compute_pagemask(arg1); in helper_mtc0_pagemask()
892 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) | in helper_mtc0_pagegrain()
893 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask); in helper_mtc0_pagegrain()
902 env->CP0_SegCtl0 = arg1 & CP0SC0_MASK; in helper_mtc0_segctl0()
910 env->CP0_SegCtl1 = arg1 & CP0SC1_MASK; in helper_mtc0_segctl1()
918 env->CP0_SegCtl2 = arg1 & CP0SC2_MASK; in helper_mtc0_segctl2()
926 uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL; in helper_mtc0_pwfield()
929 if ((env->insn_flags & ISA_MIPS_R6)) { in helper_mtc0_pwfield()
946 env->CP0_PWField = arg1 & mask; in helper_mtc0_pwfield()
949 ((env->insn_flags & ISA_MIPS_R6) && in helper_mtc0_pwfield()
951 env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) | in helper_mtc0_pwfield()
956 uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; in helper_mtc0_pwfield()
959 if ((env->insn_flags & ISA_MIPS_R6)) { in helper_mtc0_pwfield()
973 env->CP0_PWField = arg1 & mask; in helper_mtc0_pwfield()
976 ((env->insn_flags & ISA_MIPS_R6) && in helper_mtc0_pwfield()
978 env->CP0_PWField = (env->CP0_PWField & ~0x3F) | in helper_mtc0_pwfield()
987 env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL; in helper_mtc0_pwsize()
989 env->CP0_PWSize = arg1 & 0x3FFFFFFF; in helper_mtc0_pwsize()
995 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_wired()
996 if (arg1 < env->tlb->nb_tlb) { in helper_mtc0_wired()
997 env->CP0_Wired = arg1; in helper_mtc0_wired()
1000 env->CP0_Wired = arg1 % env->tlb->nb_tlb; in helper_mtc0_wired()
1008 env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F); in helper_mtc0_pwctl()
1010 env->CP0_PWCtl = (arg1 & 0x800000FF); in helper_mtc0_pwctl()
1016 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; in helper_mtc0_srsconf0()
1021 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; in helper_mtc0_srsconf1()
1026 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; in helper_mtc0_srsconf2()
1031 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; in helper_mtc0_srsconf3()
1036 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; in helper_mtc0_srsconf4()
1043 if ((env->CP0_Config1 & (1 << CP0C1_PC)) && in helper_mtc0_hwrena()
1044 (env->insn_flags & ISA_MIPS_R6)) { in helper_mtc0_hwrena()
1047 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_hwrena()
1050 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { in helper_mtc0_hwrena()
1054 env->hflags |= MIPS_HFLAG_HWRENA_ULR; in helper_mtc0_hwrena()
1056 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR; in helper_mtc0_hwrena()
1060 env->CP0_HWREna = arg1 & mask; in helper_mtc0_hwrena()
1071 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask; in helper_mtc0_entryhi()
1072 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) { in helper_mtc0_entryhi()
1078 if (env->insn_flags & ISA_MIPS_R6) { in helper_mtc0_entryhi()
1080 int config0_at = extract32(env->CP0_Config0, 13, 2); in helper_mtc0_entryhi()
1081 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0; in helper_mtc0_entryhi()
1088 mask &= env->SEGMask; in helper_mtc0_entryhi()
1090 old = env->CP0_EntryHi; in helper_mtc0_entryhi()
1092 env->CP0_EntryHi = val; in helper_mtc0_entryhi()
1094 sync_c0_entryhi(env, env->current_tc); in helper_mtc0_entryhi()
1097 if ((old & env->CP0_EntryHi_ASID_mask) != in helper_mtc0_entryhi()
1098 (val & env->CP0_EntryHi_ASID_mask)) { in helper_mtc0_entryhi()
1105 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_entryhi()
1108 other->CP0_EntryHi = arg1; in helper_mttc0_entryhi()
1121 old = env->CP0_Status; in helper_mtc0_status()
1123 val = env->CP0_Status; in helper_mtc0_status()
1127 old, old & env->CP0_Cause & CP0Ca_IP_mask, in helper_mtc0_status()
1128 val, val & env->CP0_Cause & CP0Ca_IP_mask, in helper_mtc0_status()
1129 env->CP0_Cause); in helper_mtc0_status()
1152 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_status()
1153 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018; in helper_mttc0_status()
1156 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask); in helper_mttc0_status()
1162 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0); in helper_mtc0_intctl()
1168 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); in helper_mtc0_srsctl()
1178 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_cause()
1186 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_epc()
1189 return other->CP0_EPC; in helper_mftc0_epc()
1194 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_ebase()
1197 return other->CP0_EBase; in helper_mftc0_ebase()
1202 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; in helper_mtc0_ebase()
1203 if (arg1 & env->CP0_EBaseWG_rw_bitmask) { in helper_mtc0_ebase()
1206 env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask); in helper_mtc0_ebase()
1211 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_ebase()
1213 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; in helper_mttc0_ebase()
1214 if (arg1 & env->CP0_EBaseWG_rw_bitmask) { in helper_mttc0_ebase()
1217 other->CP0_EBase = (other->CP0_EBase & ~mask) | (arg1 & mask); in helper_mttc0_ebase()
1222 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftc0_configx()
1226 case 0: return other->CP0_Config0; in helper_mftc0_configx()
1227 case 1: return other->CP0_Config1; in helper_mftc0_configx()
1228 case 2: return other->CP0_Config2; in helper_mftc0_configx()
1229 case 3: return other->CP0_Config3; in helper_mftc0_configx()
1231 case 6: return other->CP0_Config6; in helper_mftc0_configx()
1232 case 7: return other->CP0_Config7; in helper_mftc0_configx()
1241 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); in helper_mtc0_config0()
1247 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); in helper_mtc0_config2()
1252 if (env->insn_flags & ASE_MICROMIPS) { in helper_mtc0_config3()
1253 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) | in helper_mtc0_config3()
1260 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) | in helper_mtc0_config4()
1261 (arg1 & env->CP0_Config4_rw_bitmask); in helper_mtc0_config4()
1266 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) | in helper_mtc0_config5()
1267 (arg1 & env->CP0_Config5_rw_bitmask); in helper_mtc0_config5()
1268 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in helper_mtc0_config5()
1269 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; in helper_mtc0_config5()
1275 target_long mask = env->CP0_LLAddr_rw_bitmask; in helper_mtc0_lladdr()
1276 arg1 = arg1 << env->CP0_LLAddr_shift; in helper_mtc0_lladdr()
1277 env->CP0_LLAddr = (env->CP0_LLAddr & ~mask) | (arg1 & mask); in helper_mtc0_lladdr()
1281 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1285 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env); in helper_mtc0_maar()
1290 env->CP0_MAAR[env->CP0_MAARI] = in helper_mthc0_maar()
1292 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL); in helper_mthc0_maar()
1303 env->CP0_MAARI = MIPS_MAAR_MAX - 1; in helper_mtc0_maari()
1305 env->CP0_MAARI = index; in helper_mtc0_maari()
1319 env->CP0_WatchLo[sel] = (arg1 & ~0x7); in helper_mtc0_watchlo()
1324 uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID); in helper_mtc0_watchhi()
1325 uint64_t m_bit = env->CP0_WatchHi[sel] & (1 << CP0WH_M); /* read-only */ in helper_mtc0_watchhi()
1326 if ((env->CP0_Config5 >> CP0C5_MI) & 1) { in helper_mtc0_watchhi()
1329 env->CP0_WatchHi[sel] = m_bit | (arg1 & mask); in helper_mtc0_watchhi()
1330 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); in helper_mtc0_watchhi()
1335 env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) | in helper_mthc0_watchhi()
1336 (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL); in helper_mthc0_watchhi()
1341 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; in helper_mtc0_xcontext()
1342 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); in helper_mtc0_xcontext()
1347 env->CP0_Framemask = arg1; /* XXX */ in helper_mtc0_framemask()
1352 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); in helper_mtc0_debug()
1354 env->hflags |= MIPS_HFLAG_DM; in helper_mtc0_debug()
1356 env->hflags &= ~MIPS_HFLAG_DM; in helper_mtc0_debug()
1362 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttc0_debug()
1367 if (other_tc == other->current_tc) { in helper_mttc0_debug()
1368 other->active_tc.CP0_Debug_tcstatus = val; in helper_mttc0_debug()
1370 other->tcs[other_tc].CP0_Debug_tcstatus = val; in helper_mttc0_debug()
1372 other->CP0_Debug = (other->CP0_Debug & in helper_mttc0_debug()
1379 env->CP0_Performance0 = arg1 & 0x000007ff; in helper_mtc0_performance0()
1386 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0; in helper_mtc0_errctl()
1388 env->CP0_ErrCtl = wst | spr | itc; in helper_mtc0_errctl()
1391 env->hflags |= MIPS_HFLAG_ITC_CACHE; in helper_mtc0_errctl()
1393 env->hflags &= ~MIPS_HFLAG_ITC_CACHE; in helper_mtc0_errctl()
1399 if (env->hflags & MIPS_HFLAG_ITC_CACHE) { in helper_mtc0_taglo()
1403 * Tag will take care of the read-only bits. in helper_mtc0_taglo()
1405 env->CP0_TagLo = arg1; in helper_mtc0_taglo()
1407 env->CP0_TagLo = arg1 & 0xFFFFFCF6; in helper_mtc0_taglo()
1413 env->CP0_DataLo = arg1; /* XXX */ in helper_mtc0_datalo()
1418 env->CP0_TagHi = arg1; /* XXX */ in helper_mtc0_taghi()
1423 env->CP0_DataHi = arg1; /* XXX */ in helper_mtc0_datahi()
1429 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftgpr()
1432 if (other_tc == other->current_tc) { in helper_mftgpr()
1433 return other->active_tc.gpr[sel]; in helper_mftgpr()
1435 return other->tcs[other_tc].gpr[sel]; in helper_mftgpr()
1441 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftlo()
1444 if (other_tc == other->current_tc) { in helper_mftlo()
1445 return other->active_tc.LO[sel]; in helper_mftlo()
1447 return other->tcs[other_tc].LO[sel]; in helper_mftlo()
1453 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mfthi()
1456 if (other_tc == other->current_tc) { in helper_mfthi()
1457 return other->active_tc.HI[sel]; in helper_mfthi()
1459 return other->tcs[other_tc].HI[sel]; in helper_mfthi()
1465 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftacx()
1468 if (other_tc == other->current_tc) { in helper_mftacx()
1469 return other->active_tc.ACX[sel]; in helper_mftacx()
1471 return other->tcs[other_tc].ACX[sel]; in helper_mftacx()
1477 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mftdsp()
1480 if (other_tc == other->current_tc) { in helper_mftdsp()
1481 return other->active_tc.DSPControl; in helper_mftdsp()
1483 return other->tcs[other_tc].DSPControl; in helper_mftdsp()
1489 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttgpr()
1492 if (other_tc == other->current_tc) { in helper_mttgpr()
1493 other->active_tc.gpr[sel] = arg1; in helper_mttgpr()
1495 other->tcs[other_tc].gpr[sel] = arg1; in helper_mttgpr()
1501 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttlo()
1504 if (other_tc == other->current_tc) { in helper_mttlo()
1505 other->active_tc.LO[sel] = arg1; in helper_mttlo()
1507 other->tcs[other_tc].LO[sel] = arg1; in helper_mttlo()
1513 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mtthi()
1516 if (other_tc == other->current_tc) { in helper_mtthi()
1517 other->active_tc.HI[sel] = arg1; in helper_mtthi()
1519 other->tcs[other_tc].HI[sel] = arg1; in helper_mtthi()
1525 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttacx()
1528 if (other_tc == other->current_tc) { in helper_mttacx()
1529 other->active_tc.ACX[sel] = arg1; in helper_mttacx()
1531 other->tcs[other_tc].ACX[sel] = arg1; in helper_mttacx()
1537 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in helper_mttdsp()
1540 if (other_tc == other->current_tc) { in helper_mttdsp()
1541 other->active_tc.DSPControl = arg1; in helper_mttdsp()
1543 other->tcs[other_tc].DSPControl = arg1; in helper_mttdsp()
1563 target_ulong prev = env->mvp->CP0_MVPControl; in helper_dvpe()
1568 if (&other_cpu->env != env) { in helper_dvpe()
1569 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); in helper_dvpe()
1579 target_ulong prev = env->mvp->CP0_MVPControl; in helper_evpe()
1584 if (&other_cpu->env != env in helper_evpe()
1588 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); in helper_evpe()
1595 /* R6 Multi-threading */
1599 target_ulong prev = env->CP0_VPControl; in helper_dvp()
1601 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) { in helper_dvp()
1605 if (&other_cpu->env != env) { in helper_dvp()
1609 env->CP0_VPControl |= (1 << CP0VPCtl_DIS); in helper_dvp()
1617 target_ulong prev = env->CP0_VPControl; in helper_evp()
1619 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { in helper_evp()
1622 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) { in helper_evp()
1630 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS); in helper_evp()