Lines Matching +full:enum +full:- +full:as +full:- +full:flags

2  * Decode table flags, mostly based on Intel SDM.
10 * License as published by the Free Software Foundation; either
22 typedef enum X86OpType {
35 X86_TYPE_L, /* The upper 4 bits of the immediate select a 128-bit register */
52 X86_TYPE_I_unsigned, /* Immediate, zero-extended */
53 X86_TYPE_nop, /* modrm operand decoded but not loaded into s->T{0,1} */
54 X86_TYPE_2op, /* 2-operand RMW instruction */
55 X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */
56 X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */
64 X86_TYPE_ES, /* Hard-coded segment registers */
72 typedef enum X86OpSize {
77 X86_SIZE_d, /* 32-bit */
78 X86_SIZE_dq, /* SSE/AVX 128-bit */
83 X86_SIZE_q, /* 64-bit */
84 X86_SIZE_qq, /* AVX 256-bit */
88 X86_SIZE_si, /* 32-bit GPR */
89 X86_SIZE_v, /* 16/32/64-bit, based on operand size */
90 X86_SIZE_w, /* 16-bit */
91 X86_SIZE_x, /* 128/256-bit, based on operand size */
92 X86_SIZE_y, /* 32/64-bit, based on operand size */
93 X86_SIZE_y_d64, /* 32/64-bit, based on 64-bit mode */
94 X86_SIZE_z, /* 16-bit for 16-bit operand size, else 32-bit */
95 X86_SIZE_z_f64, /* 32-bit for 32-bit operand size or 64-bit mode, else 16-bit */
103 typedef enum X86CPUIDFeature {
138 /* Execution flags */
140 typedef enum X86OpUnit {
145 X86_OP_INT, /* loaded into/stored from s->T0/T1 */
147 X86_OP_SSE, /* address in either s->ptrX or s->A0 depending on has_ea */
148 X86_OP_MMX, /* address in either s->ptrX or s->A0 depending on has_ea */
151 typedef enum X86InsnCheck {
152 /* Illegal or exclusive to 64-bit mode */
181 /* Vendor-specific checks for Intel/AMD differences */
186 typedef enum X86InsnSpecial {
198 /* Do not load effective address in s->A0 */
202 * Rd/Mb or Rd/Mw in the manual: register operand 0 is treated as 32 bits
203 * (and writeback zero-extends it to 64 bits if applicable). PREFIX_DATA
204 * does not trigger 16-bit writeback and, as a side effect, high-byte
212 * of this modifier is that high-byte registers are never used, even without
229 /* When loaded into s->T0, register operand 1 is zero/sign extended. */
244 typedef enum X86VEXSpecial {
258 * VEX instructions that only support 256-bit operands with AVX2 (Table 2-17
259 * column 3). Columns 2 and 4 (instructions limited to 256- and 127-bit
278 /* Based on the is_decode flags. */
335 * one (and also for 4-operand instructions).