Lines Matching full:state
86 struct nvmm_x64_state *state = vcpu->state; in nvmm_set_registers() local
94 state->gprs[NVMM_X64_GPR_RAX] = env->regs[R_EAX]; in nvmm_set_registers()
95 state->gprs[NVMM_X64_GPR_RCX] = env->regs[R_ECX]; in nvmm_set_registers()
96 state->gprs[NVMM_X64_GPR_RDX] = env->regs[R_EDX]; in nvmm_set_registers()
97 state->gprs[NVMM_X64_GPR_RBX] = env->regs[R_EBX]; in nvmm_set_registers()
98 state->gprs[NVMM_X64_GPR_RSP] = env->regs[R_ESP]; in nvmm_set_registers()
99 state->gprs[NVMM_X64_GPR_RBP] = env->regs[R_EBP]; in nvmm_set_registers()
100 state->gprs[NVMM_X64_GPR_RSI] = env->regs[R_ESI]; in nvmm_set_registers()
101 state->gprs[NVMM_X64_GPR_RDI] = env->regs[R_EDI]; in nvmm_set_registers()
103 state->gprs[NVMM_X64_GPR_R8] = env->regs[R_R8]; in nvmm_set_registers()
104 state->gprs[NVMM_X64_GPR_R9] = env->regs[R_R9]; in nvmm_set_registers()
105 state->gprs[NVMM_X64_GPR_R10] = env->regs[R_R10]; in nvmm_set_registers()
106 state->gprs[NVMM_X64_GPR_R11] = env->regs[R_R11]; in nvmm_set_registers()
107 state->gprs[NVMM_X64_GPR_R12] = env->regs[R_R12]; in nvmm_set_registers()
108 state->gprs[NVMM_X64_GPR_R13] = env->regs[R_R13]; in nvmm_set_registers()
109 state->gprs[NVMM_X64_GPR_R14] = env->regs[R_R14]; in nvmm_set_registers()
110 state->gprs[NVMM_X64_GPR_R15] = env->regs[R_R15]; in nvmm_set_registers()
114 state->gprs[NVMM_X64_GPR_RIP] = env->eip; in nvmm_set_registers()
115 state->gprs[NVMM_X64_GPR_RFLAGS] = env->eflags; in nvmm_set_registers()
118 nvmm_set_segment(&state->segs[NVMM_X64_SEG_CS], &env->segs[R_CS]); in nvmm_set_registers()
119 nvmm_set_segment(&state->segs[NVMM_X64_SEG_DS], &env->segs[R_DS]); in nvmm_set_registers()
120 nvmm_set_segment(&state->segs[NVMM_X64_SEG_ES], &env->segs[R_ES]); in nvmm_set_registers()
121 nvmm_set_segment(&state->segs[NVMM_X64_SEG_FS], &env->segs[R_FS]); in nvmm_set_registers()
122 nvmm_set_segment(&state->segs[NVMM_X64_SEG_GS], &env->segs[R_GS]); in nvmm_set_registers()
123 nvmm_set_segment(&state->segs[NVMM_X64_SEG_SS], &env->segs[R_SS]); in nvmm_set_registers()
126 nvmm_set_segment(&state->segs[NVMM_X64_SEG_GDT], &env->gdt); in nvmm_set_registers()
127 nvmm_set_segment(&state->segs[NVMM_X64_SEG_LDT], &env->ldt); in nvmm_set_registers()
128 nvmm_set_segment(&state->segs[NVMM_X64_SEG_TR], &env->tr); in nvmm_set_registers()
129 nvmm_set_segment(&state->segs[NVMM_X64_SEG_IDT], &env->idt); in nvmm_set_registers()
132 state->crs[NVMM_X64_CR_CR0] = env->cr[0]; in nvmm_set_registers()
133 state->crs[NVMM_X64_CR_CR2] = env->cr[2]; in nvmm_set_registers()
134 state->crs[NVMM_X64_CR_CR3] = env->cr[3]; in nvmm_set_registers()
135 state->crs[NVMM_X64_CR_CR4] = env->cr[4]; in nvmm_set_registers()
136 state->crs[NVMM_X64_CR_CR8] = qcpu->tpr; in nvmm_set_registers()
137 state->crs[NVMM_X64_CR_XCR0] = env->xcr0; in nvmm_set_registers()
140 state->drs[NVMM_X64_DR_DR0] = env->dr[0]; in nvmm_set_registers()
141 state->drs[NVMM_X64_DR_DR1] = env->dr[1]; in nvmm_set_registers()
142 state->drs[NVMM_X64_DR_DR2] = env->dr[2]; in nvmm_set_registers()
143 state->drs[NVMM_X64_DR_DR3] = env->dr[3]; in nvmm_set_registers()
144 state->drs[NVMM_X64_DR_DR6] = env->dr[6]; in nvmm_set_registers()
145 state->drs[NVMM_X64_DR_DR7] = env->dr[7]; in nvmm_set_registers()
148 state->fpu.fx_cw = env->fpuc; in nvmm_set_registers()
149 state->fpu.fx_sw = (env->fpus & ~0x3800) | ((env->fpstt & 0x7) << 11); in nvmm_set_registers()
150 state->fpu.fx_tw = 0; in nvmm_set_registers()
152 state->fpu.fx_tw |= (!env->fptags[i]) << i; in nvmm_set_registers()
154 state->fpu.fx_opcode = env->fpop; in nvmm_set_registers()
155 state->fpu.fx_ip.fa_64 = env->fpip; in nvmm_set_registers()
156 state->fpu.fx_dp.fa_64 = env->fpdp; in nvmm_set_registers()
157 state->fpu.fx_mxcsr = env->mxcsr; in nvmm_set_registers()
158 state->fpu.fx_mxcsr_mask = 0x0000FFFF; in nvmm_set_registers()
159 assert(sizeof(state->fpu.fx_87_ac) == sizeof(env->fpregs)); in nvmm_set_registers()
160 memcpy(state->fpu.fx_87_ac, env->fpregs, sizeof(env->fpregs)); in nvmm_set_registers()
162 memcpy(&state->fpu.fx_xmm[i].xmm_bytes[0], in nvmm_set_registers()
164 memcpy(&state->fpu.fx_xmm[i].xmm_bytes[8], in nvmm_set_registers()
169 state->msrs[NVMM_X64_MSR_EFER] = env->efer; in nvmm_set_registers()
170 state->msrs[NVMM_X64_MSR_STAR] = env->star; in nvmm_set_registers()
172 state->msrs[NVMM_X64_MSR_LSTAR] = env->lstar; in nvmm_set_registers()
173 state->msrs[NVMM_X64_MSR_CSTAR] = env->cstar; in nvmm_set_registers()
174 state->msrs[NVMM_X64_MSR_SFMASK] = env->fmask; in nvmm_set_registers()
175 state->msrs[NVMM_X64_MSR_KERNELGSBASE] = env->kernelgsbase; in nvmm_set_registers()
177 state->msrs[NVMM_X64_MSR_SYSENTER_CS] = env->sysenter_cs; in nvmm_set_registers()
178 state->msrs[NVMM_X64_MSR_SYSENTER_ESP] = env->sysenter_esp; in nvmm_set_registers()
179 state->msrs[NVMM_X64_MSR_SYSENTER_EIP] = env->sysenter_eip; in nvmm_set_registers()
180 state->msrs[NVMM_X64_MSR_PAT] = env->pat; in nvmm_set_registers()
181 state->msrs[NVMM_X64_MSR_TSC] = env->tsc; in nvmm_set_registers()
224 struct nvmm_x64_state *state = vcpu->state; in nvmm_get_registers() local
246 env->regs[R_EAX] = state->gprs[NVMM_X64_GPR_RAX]; in nvmm_get_registers()
247 env->regs[R_ECX] = state->gprs[NVMM_X64_GPR_RCX]; in nvmm_get_registers()
248 env->regs[R_EDX] = state->gprs[NVMM_X64_GPR_RDX]; in nvmm_get_registers()
249 env->regs[R_EBX] = state->gprs[NVMM_X64_GPR_RBX]; in nvmm_get_registers()
250 env->regs[R_ESP] = state->gprs[NVMM_X64_GPR_RSP]; in nvmm_get_registers()
251 env->regs[R_EBP] = state->gprs[NVMM_X64_GPR_RBP]; in nvmm_get_registers()
252 env->regs[R_ESI] = state->gprs[NVMM_X64_GPR_RSI]; in nvmm_get_registers()
253 env->regs[R_EDI] = state->gprs[NVMM_X64_GPR_RDI]; in nvmm_get_registers()
255 env->regs[R_R8] = state->gprs[NVMM_X64_GPR_R8]; in nvmm_get_registers()
256 env->regs[R_R9] = state->gprs[NVMM_X64_GPR_R9]; in nvmm_get_registers()
257 env->regs[R_R10] = state->gprs[NVMM_X64_GPR_R10]; in nvmm_get_registers()
258 env->regs[R_R11] = state->gprs[NVMM_X64_GPR_R11]; in nvmm_get_registers()
259 env->regs[R_R12] = state->gprs[NVMM_X64_GPR_R12]; in nvmm_get_registers()
260 env->regs[R_R13] = state->gprs[NVMM_X64_GPR_R13]; in nvmm_get_registers()
261 env->regs[R_R14] = state->gprs[NVMM_X64_GPR_R14]; in nvmm_get_registers()
262 env->regs[R_R15] = state->gprs[NVMM_X64_GPR_R15]; in nvmm_get_registers()
266 env->eip = state->gprs[NVMM_X64_GPR_RIP]; in nvmm_get_registers()
267 env->eflags = state->gprs[NVMM_X64_GPR_RFLAGS]; in nvmm_get_registers()
270 nvmm_get_segment(&env->segs[R_ES], &state->segs[NVMM_X64_SEG_ES]); in nvmm_get_registers()
271 nvmm_get_segment(&env->segs[R_CS], &state->segs[NVMM_X64_SEG_CS]); in nvmm_get_registers()
272 nvmm_get_segment(&env->segs[R_SS], &state->segs[NVMM_X64_SEG_SS]); in nvmm_get_registers()
273 nvmm_get_segment(&env->segs[R_DS], &state->segs[NVMM_X64_SEG_DS]); in nvmm_get_registers()
274 nvmm_get_segment(&env->segs[R_FS], &state->segs[NVMM_X64_SEG_FS]); in nvmm_get_registers()
275 nvmm_get_segment(&env->segs[R_GS], &state->segs[NVMM_X64_SEG_GS]); in nvmm_get_registers()
278 nvmm_get_segment(&env->gdt, &state->segs[NVMM_X64_SEG_GDT]); in nvmm_get_registers()
279 nvmm_get_segment(&env->ldt, &state->segs[NVMM_X64_SEG_LDT]); in nvmm_get_registers()
280 nvmm_get_segment(&env->tr, &state->segs[NVMM_X64_SEG_TR]); in nvmm_get_registers()
281 nvmm_get_segment(&env->idt, &state->segs[NVMM_X64_SEG_IDT]); in nvmm_get_registers()
284 env->cr[0] = state->crs[NVMM_X64_CR_CR0]; in nvmm_get_registers()
285 env->cr[2] = state->crs[NVMM_X64_CR_CR2]; in nvmm_get_registers()
286 env->cr[3] = state->crs[NVMM_X64_CR_CR3]; in nvmm_get_registers()
287 env->cr[4] = state->crs[NVMM_X64_CR_CR4]; in nvmm_get_registers()
288 tpr = state->crs[NVMM_X64_CR_CR8]; in nvmm_get_registers()
293 env->xcr0 = state->crs[NVMM_X64_CR_XCR0]; in nvmm_get_registers()
296 env->dr[0] = state->drs[NVMM_X64_DR_DR0]; in nvmm_get_registers()
297 env->dr[1] = state->drs[NVMM_X64_DR_DR1]; in nvmm_get_registers()
298 env->dr[2] = state->drs[NVMM_X64_DR_DR2]; in nvmm_get_registers()
299 env->dr[3] = state->drs[NVMM_X64_DR_DR3]; in nvmm_get_registers()
300 env->dr[6] = state->drs[NVMM_X64_DR_DR6]; in nvmm_get_registers()
301 env->dr[7] = state->drs[NVMM_X64_DR_DR7]; in nvmm_get_registers()
304 env->fpuc = state->fpu.fx_cw; in nvmm_get_registers()
305 env->fpstt = (state->fpu.fx_sw >> 11) & 0x7; in nvmm_get_registers()
306 env->fpus = state->fpu.fx_sw & ~0x3800; in nvmm_get_registers()
308 env->fptags[i] = !((state->fpu.fx_tw >> i) & 1); in nvmm_get_registers()
310 env->fpop = state->fpu.fx_opcode; in nvmm_get_registers()
311 env->fpip = state->fpu.fx_ip.fa_64; in nvmm_get_registers()
312 env->fpdp = state->fpu.fx_dp.fa_64; in nvmm_get_registers()
313 env->mxcsr = state->fpu.fx_mxcsr; in nvmm_get_registers()
314 assert(sizeof(state->fpu.fx_87_ac) == sizeof(env->fpregs)); in nvmm_get_registers()
315 memcpy(env->fpregs, state->fpu.fx_87_ac, sizeof(env->fpregs)); in nvmm_get_registers()
318 &state->fpu.fx_xmm[i].xmm_bytes[0], 8); in nvmm_get_registers()
320 &state->fpu.fx_xmm[i].xmm_bytes[8], 8); in nvmm_get_registers()
324 env->efer = state->msrs[NVMM_X64_MSR_EFER]; in nvmm_get_registers()
325 env->star = state->msrs[NVMM_X64_MSR_STAR]; in nvmm_get_registers()
327 env->lstar = state->msrs[NVMM_X64_MSR_LSTAR]; in nvmm_get_registers()
328 env->cstar = state->msrs[NVMM_X64_MSR_CSTAR]; in nvmm_get_registers()
329 env->fmask = state->msrs[NVMM_X64_MSR_SFMASK]; in nvmm_get_registers()
330 env->kernelgsbase = state->msrs[NVMM_X64_MSR_KERNELGSBASE]; in nvmm_get_registers()
332 env->sysenter_cs = state->msrs[NVMM_X64_MSR_SYSENTER_CS]; in nvmm_get_registers()
333 env->sysenter_esp = state->msrs[NVMM_X64_MSR_SYSENTER_ESP]; in nvmm_get_registers()
334 env->sysenter_eip = state->msrs[NVMM_X64_MSR_SYSENTER_EIP]; in nvmm_get_registers()
335 env->pat = state->msrs[NVMM_X64_MSR_PAT]; in nvmm_get_registers()
336 env->tsc = state->msrs[NVMM_X64_MSR_TSC]; in nvmm_get_registers()
353 struct nvmm_x64_state *state = vcpu->state; in nvmm_can_take_int() local
357 state->intr.int_window_exiting = 1; in nvmm_can_take_int()
395 struct nvmm_x64_state *state = vcpu->state; in nvmm_vcpu_pre_run() local
444 error_report("NVMM: Failed to get CPU state," in nvmm_vcpu_pre_run()
448 state->crs[NVMM_X64_CR_CR8] = qcpu->tpr; in nvmm_vcpu_pre_run()
452 error_report("NVMM: Failed to set CPU state," in nvmm_vcpu_pre_run()
565 struct nvmm_x64_state *state = vcpu->state; in nvmm_handle_rdmsr() local
591 state->gprs[NVMM_X64_GPR_RAX] = (val & 0xFFFFFFFF); in nvmm_handle_rdmsr()
592 state->gprs[NVMM_X64_GPR_RDX] = (val >> 32); in nvmm_handle_rdmsr()
593 state->gprs[NVMM_X64_GPR_RIP] = exit->u.rdmsr.npc; in nvmm_handle_rdmsr()
610 struct nvmm_x64_state *state = vcpu->state; in nvmm_handle_wrmsr() local
634 state->gprs[NVMM_X64_GPR_RIP] = exit->u.wrmsr.npc; in nvmm_handle_wrmsr()
695 /* set int/nmi windows back to the reset state */ in nvmm_vcpu_loop()
1178 error_report("NVMM: Wrong state size %u", qemu_mach.cap.state_size); in nvmm_accel_init()