Lines Matching +full:cross +full:- +full:i386 +full:- +full:system
2 * i386 CPUID, CPU class, definitions, models
23 #include "qemu/qemu-print.h"
24 #include "qemu/hw-version.h"
26 #include "tcg/helper-tcg.h"
27 #include "exec/translation-block.h"
28 #include "system/hvf.h"
29 #include "hvf/hvf-i386.h"
33 #include "qemu/error-report.h"
34 #include "qapi/qapi-visit-machine.h"
35 #include "standard-headers/asm-x86/kvm_para.h"
36 #include "hw/qdev-properties.h"
37 #include "hw/i386/topology.h"
40 #include "confidential-guest.h"
41 #include "system/reset.h"
42 #include "qapi/qapi-commands-machine.h"
43 #include "system/address-spaces.h"
45 #include "hw/i386/sgx-epc.h"
47 #include "tcg/tcg-cpu.h"
50 #include "cpu-internal.h"
206 assert(cache->size > 0); in cpuid2_cache_descriptor()
207 assert(cache->level > 0); in cpuid2_cache_descriptor()
208 assert(cache->line_size > 0); in cpuid2_cache_descriptor()
209 assert(cache->associativity > 0); in cpuid2_cache_descriptor()
212 if (d->level == cache->level && d->type == cache->type && in cpuid2_cache_descriptor()
213 d->size == cache->size && d->line_size == cache->line_size && in cpuid2_cache_descriptor()
214 d->associativity == cache->associativity) { in cpuid2_cache_descriptor()
270 return num_ids - 1; in max_thread_ids_for_cache()
275 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - in max_core_ids_in_package()
277 return num_cores - 1; in max_core_ids_in_package()
286 assert(cache->size == cache->line_size * cache->associativity * in encode_cache_cpuid4()
287 cache->partitions * cache->sets); in encode_cache_cpuid4()
289 *eax = CACHE_TYPE(cache->type) | in encode_cache_cpuid4()
290 CACHE_LEVEL(cache->level) | in encode_cache_cpuid4()
291 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | in encode_cache_cpuid4()
293 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); in encode_cache_cpuid4()
295 assert(cache->line_size > 0); in encode_cache_cpuid4()
296 assert(cache->partitions > 0); in encode_cache_cpuid4()
297 assert(cache->associativity > 0); in encode_cache_cpuid4()
298 /* We don't implement fully-associative caches */ in encode_cache_cpuid4()
299 assert(cache->associativity < cache->sets); in encode_cache_cpuid4()
300 *ebx = (cache->line_size - 1) | in encode_cache_cpuid4()
301 ((cache->partitions - 1) << 12) | in encode_cache_cpuid4()
302 ((cache->associativity - 1) << 22); in encode_cache_cpuid4()
304 assert(cache->sets > 0); in encode_cache_cpuid4()
305 *ecx = cache->sets - 1; in encode_cache_cpuid4()
307 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | in encode_cache_cpuid4()
308 (cache->inclusive ? CACHE_INCLUSIVE : 0) | in encode_cache_cpuid4()
309 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); in encode_cache_cpuid4()
319 return topo_info->threads_per_core; in num_threads_by_topo_level()
390 level = find_next_bit(env->avail_cpu_topo, in encode_topo_cpuid1f()
411 next_level = find_next_bit(env->avail_cpu_topo, in encode_topo_cpuid1f()
421 /* The count (bits 15-00) doesn't need to be reliable. */ in encode_topo_cpuid1f()
424 *edx = cpu->apic_id; in encode_topo_cpuid1f()
432 assert(cache->size % 1024 == 0); in encode_cache_cpuid80000005()
433 assert(cache->lines_per_tag > 0); in encode_cache_cpuid80000005()
434 assert(cache->associativity > 0); in encode_cache_cpuid80000005()
435 assert(cache->line_size > 0); in encode_cache_cpuid80000005()
436 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | in encode_cache_cpuid80000005()
437 (cache->lines_per_tag << 8) | (cache->line_size); in encode_cache_cpuid80000005()
464 assert(l2->size % 1024 == 0); in encode_cache_cpuid80000006()
465 assert(l2->associativity > 0); in encode_cache_cpuid80000006()
466 assert(l2->lines_per_tag > 0); in encode_cache_cpuid80000006()
467 assert(l2->line_size > 0); in encode_cache_cpuid80000006()
468 *ecx = ((l2->size / 1024) << 16) | in encode_cache_cpuid80000006()
469 (AMD_ENC_ASSOC(l2->associativity) << 12) | in encode_cache_cpuid80000006()
470 (l2->lines_per_tag << 8) | (l2->line_size); in encode_cache_cpuid80000006()
473 assert(l3->size % (512 * 1024) == 0); in encode_cache_cpuid80000006()
474 assert(l3->associativity > 0); in encode_cache_cpuid80000006()
475 assert(l3->lines_per_tag > 0); in encode_cache_cpuid80000006()
476 assert(l3->line_size > 0); in encode_cache_cpuid80000006()
477 *edx = ((l3->size / (512 * 1024)) << 18) | in encode_cache_cpuid80000006()
478 (AMD_ENC_ASSOC(l3->associativity) << 12) | in encode_cache_cpuid80000006()
479 (l3->lines_per_tag << 8) | (l3->line_size); in encode_cache_cpuid80000006()
491 assert(cache->size == cache->line_size * cache->associativity * in encode_cache_cpuid8000001d()
492 cache->partitions * cache->sets); in encode_cache_cpuid8000001d()
494 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | in encode_cache_cpuid8000001d()
495 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); in encode_cache_cpuid8000001d()
496 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; in encode_cache_cpuid8000001d()
498 assert(cache->line_size > 0); in encode_cache_cpuid8000001d()
499 assert(cache->partitions > 0); in encode_cache_cpuid8000001d()
500 assert(cache->associativity > 0); in encode_cache_cpuid8000001d()
501 /* We don't implement fully-associative caches */ in encode_cache_cpuid8000001d()
502 assert(cache->associativity < cache->sets); in encode_cache_cpuid8000001d()
503 *ebx = (cache->line_size - 1) | in encode_cache_cpuid8000001d()
504 ((cache->partitions - 1) << 12) | in encode_cache_cpuid8000001d()
505 ((cache->associativity - 1) << 22); in encode_cache_cpuid8000001d()
507 assert(cache->sets > 0); in encode_cache_cpuid8000001d()
508 *ecx = cache->sets - 1; in encode_cache_cpuid8000001d()
510 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | in encode_cache_cpuid8000001d()
511 (cache->inclusive ? CACHE_INCLUSIVE : 0) | in encode_cache_cpuid8000001d()
512 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); in encode_cache_cpuid8000001d()
522 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); in encode_topo_cpuid8000001e()
524 *eax = cpu->apic_id; in encode_topo_cpuid8000001e()
528 * Read-only. Reset: 0000_XXXXh. in encode_topo_cpuid8000001e()
533 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. in encode_topo_cpuid8000001e()
535 * 7:0 CoreId: core ID. Read-only. Reset: XXh. in encode_topo_cpuid8000001e()
540 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); in encode_topo_cpuid8000001e()
544 * Read-only. Reset: 0000_0XXXh. in encode_topo_cpuid8000001e()
548 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. in encode_topo_cpuid8000001e()
552 * 7h-1h Reserved. in encode_topo_cpuid8000001e()
553 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. in encode_topo_cpuid8000001e()
561 if (cpu->legacy_multi_node) { in encode_topo_cpuid8000001e()
562 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | in encode_topo_cpuid8000001e()
563 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); in encode_topo_cpuid8000001e()
565 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; in encode_topo_cpuid8000001e()
716 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
719 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
729 * bit[02]: Support Single-Range Output scheme;
788 * Kernel-only features that can be shown to usermode programs even if
789 * they aren't actually supported by TCG, because qemu-user only runs
790 * in CPL=3; remove them if they are ever implemented for system emulation.
820 * in usermode or by 32-bit programs. Those are added to supported
821 * TCG features unconditionally in user-mode emulation mode. This may
825 * Even for long mode, qemu-i386 is not running "a userspace program on a
826 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment"
827 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit
833 /* FIXME: Long mode not yet supported for i386 bsd-user */
961 "ds-cpl", "vmx", "smx", "est",
966 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
986 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
995 "lahf-lm", "cmp-legacy", "svm", "extapic",
999 "fma4", "tce", NULL, "nodeid-msr",
1000 NULL, "tbm", "topoext", "perfctr-core",
1001 "perfctr-nb", NULL, NULL, NULL,
1008 * "-cpu host", as it requires consistent cache topology info
1016 NULL, NULL, "xstore", "xstore-en",
1017 NULL, NULL, "xcrypt", "xcrypt-en",
1018 "ace2", "ace2-en", "phe", "phe-en",
1019 "pmm", "pmm-en", NULL, NULL,
1031 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
1032 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
1033 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi",
1034 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
1037 "kvmclock-stable-bit", NULL, NULL, NULL,
1046 "kvm-hint-dedicated", NULL, NULL, NULL,
1058 * KVM hints aren't auto-enabled by -cpu host, they need to be
1059 * explicitly enabled in the command-line.
1066 "npt", "lbrv", "svm-lock", "nrip-save",
1067 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1068 NULL, NULL, "pause-filter", NULL,
1069 "pfthreshold", "avic", NULL, "v-vmsave-vmload",
1073 "svme-addr-chk", NULL, NULL, NULL,
1081 "fsgsbase", "tsc-adjust", "sgx", "bmi1",
1082 "hle", "avx2", "fdp-excptn-only", "smep",
1084 NULL, "zero-fcs-fds", "mpx", NULL,
1087 "clwb", "intel-pt", "avx512pf", "avx512er",
1088 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1103 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
1106 "bus-lock-detect", "cldemote", NULL, "movdiri",
1119 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1121 "avx512-vp2intersect", NULL, "md-clear", NULL,
1123 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr",
1124 NULL, NULL, "amx-bf16", "avx512-fp16",
1125 "amx-tile", "amx-int8", "spec-ctrl", "stibp",
1126 "flush-l1d", "arch-capabilities", "core-capability", "ssbd",
1139 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
1143 NULL, "amx-fp16", NULL, "avx-ifma",
1158 NULL, "msr-imm", NULL, NULL,
1177 "avx-vnni-int8", "avx-ne-convert", NULL, NULL,
1178 "amx-complex", NULL, "avx-vnni-int16", NULL,
1195 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u",
1196 "bhi-ctrl", "mcdt-no", NULL, NULL,
1214 [16] = "avx10-128",
1215 [17] = "avx10-256",
1216 [18] = "avx10-512",
1244 "overflow-recov", "succor", NULL, NULL,
1263 "ibpb", NULL, "ibrs", "amd-stibp",
1264 NULL, "stibp-always-on", NULL, NULL,
1266 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1267 "amd-psfd", NULL, NULL, NULL,
1276 "no-nested-data-bp", "fs-gs-base-ns", "lfence-always-serializing", NULL,
1277 NULL, NULL, "null-sel-clr-base", NULL,
1278 "auto-ibrs", NULL, NULL, NULL,
1283 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL,
1298 "perfmon-v2", NULL, NULL, NULL,
1401 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1402 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1403 "taa-no", NULL, NULL, NULL,
1404 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no",
1405 NULL, "fb-clear", NULL, NULL,
1406 "bhi-no", NULL, NULL, NULL,
1407 "pbrsb-no", NULL, "gds-no", "rfds-no",
1408 "rfds-clear", NULL, NULL, NULL,
1416 NULL, NULL, "its-no", NULL,
1422 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which
1424 > on any user-mode operation, and warnings about unsupported
1433 NULL, "split-lock-detect", NULL, NULL,
1451 NULL, "full-width-write", NULL, NULL,
1465 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1466 NULL, NULL, NULL, "vmx-hlt-exit",
1467 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1468 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1469 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1470 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1471 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1472 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1482 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1483 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1484 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1485 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1486 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1487 "vmx-xsaves", NULL, NULL, NULL,
1488 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL,
1499 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1500 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1520 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1522 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1523 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1524 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1525 "vmx-exit-save-efer", "vmx-exit-load-efer",
1526 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1527 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1528 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls",
1538 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1540 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1541 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1542 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1543 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred",
1556 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1557 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1562 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1572 "vmx-ept-execonly", NULL, NULL, NULL,
1573 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1576 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1577 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1578 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1580 "vmx-invvpid", NULL, NULL, NULL,
1582 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1583 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1598 [54] = "vmx-ins-outs",
1599 [55] = "vmx-true-ctls",
1600 [56] = "vmx-any-errcode",
1601 [58] = "vmx-nested-exception",
1606 /* Just to be safe - we don't support setting the MSEG version field. */
1613 [0] = "vmx-eptp-switching",
1630 NULL, NULL, NULL, "intel-pt-lip",
1645 NULL, NULL, NULL, "sgx-edeccssa",
1663 "sgx-exinfo" , NULL, NULL, NULL,
1683 NULL, "sgx-debug", "sgx-mode64", NULL,
1684 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
1685 NULL, NULL, "sgx-aex-notify", NULL,
1708 if (wi->type == CPUID_FEATURE_WORD && wi->cpuid.eax == feature && in is_feature_word_cpuid()
1709 (!wi->cpuid.needs_ecx || wi->cpuid.ecx == index) && in is_feature_word_cpuid()
1710 wi->cpuid.reg == reg) { in is_feature_word_cpuid()
1937 offset = compacted ? ret : esa->offset; in xsave_area_size()
1938 ret = MAX(ret, offset + esa->size); in xsave_area_size()
1951 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | in x86_cpu_xsave_xcr0_components()
1952 cpu->env.features[FEAT_XSAVE_XCR0_LO]; in x86_cpu_xsave_xcr0_components()
1955 /* Return name of 32-bit register, from a R_* constant */
1966 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | in x86_cpu_xsave_xss_components()
1967 cpu->env.features[FEAT_XSAVE_XSS_LO]; in x86_cpu_xsave_xss_components()
1977 CPUX86State *env = &cpu->env; in x86_cpu_get_migratable_flags()
1986 if ((wi->migratable_flags & f) || in x86_cpu_get_migratable_flags()
1987 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { in x86_cpu_get_migratable_flags()
1992 /* when tsc-khz is set explicitly, invtsc is migratable */ in x86_cpu_get_migratable_flags()
1993 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { in x86_cpu_get_migratable_flags()
2070 /* vendor is zero-terminated, 12 character ASCII string */
2097 * This matters only for "-cpu help" and query-cpu-definitions
2107 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); in x86_cpu_versioned_model_name()
2119 return def->versions ?: default_version_list; in x86_cpu_def_get_versions()
2773 * Dual-monitor support (all processors)
2775 * Deactivate dual-monitor treatment
2776 * Number of CR3-target values
2778 * Wait-for-SIPI activity state
2779 * PAUSE-loop exiting (Westmere and newer)
2780 * EPT-violation #VE (Broadwell and newer)
2782 * Conceal non-root operation from PT
2786 * Mode-based execute control (XS/XU)
2793 * Advanced VM-exit information for EPT violations
2794 * Sub-page write permissions
2849 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
2976 .model_id = "Common 32-bit KVM processor"
3249 .alias = "Nehalem-IBRS",
3251 { "spec-ctrl", "on" },
3252 { "model-id",
3325 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
3330 .alias = "Westmere-IBRS",
3332 { "spec-ctrl", "on" },
3333 { "model-id",
3416 .alias = "SandyBridge-IBRS",
3418 { "spec-ctrl", "on" },
3419 { "model-id",
3503 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
3508 .alias = "IvyBridge-IBRS",
3510 { "spec-ctrl", "on" },
3511 { "model-id",
3512 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
3605 .alias = "Haswell-noTSX",
3610 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
3616 .alias = "Haswell-IBRS",
3618 /* Restore TSX features removed by -v2 above */
3622 * Haswell and Haswell-IBRS had stepping=4 in
3626 { "spec-ctrl", "on" },
3627 { "model-id",
3634 .alias = "Haswell-noTSX-IBRS",
3638 /* spec-ctrl was already enabled by -v3 above */
3640 { "model-id",
3736 .alias = "Broadwell-noTSX",
3740 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
3746 .alias = "Broadwell-IBRS",
3748 /* Restore TSX features removed by -v2 above */
3751 { "spec-ctrl", "on" },
3752 { "model-id",
3759 .alias = "Broadwell-noTSX-IBRS",
3763 /* spec-ctrl was already enabled by -v3 above */
3764 { "model-id",
3773 .name = "Skylake-Client",
3809 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3860 .alias = "Skylake-Client-IBRS",
3862 { "spec-ctrl", "on" },
3863 { "model-id",
3870 .alias = "Skylake-Client-noTSX-IBRS",
3874 { "model-id",
3884 { "vmx-xsaves", "on" },
3892 .name = "Skylake-Server",
3933 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3986 .alias = "Skylake-Server-IBRS",
3988 /* clflushopt was not added to Skylake-Server-IBRS */
3989 /* TODO: add -v3 including clflushopt */
3991 { "spec-ctrl", "on" },
3992 { "model-id",
3999 .alias = "Skylake-Server-noTSX-IBRS",
4003 { "model-id",
4012 { "vmx-eptp-switching", "on" },
4021 { "vmx-xsaves", "on" },
4029 .name = "Cascadelake-Server",
4073 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4127 { "arch-capabilities", "on" },
4128 { "rdctl-no", "on" },
4129 { "ibrs-all", "on" },
4130 { "skip-l1dfl-vmentry", "on" },
4131 { "mds-no", "on" },
4136 .alias = "Cascadelake-Server-noTSX",
4147 { "vmx-eptp-switching", "on" },
4155 { "vmx-xsaves", "on" },
4214 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4270 { "vmx-xsaves", "on" },
4278 .name = "Icelake-Server",
4327 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4380 .alias = "Icelake-Server-noTSX",
4390 { "arch-capabilities", "on" },
4391 { "rdctl-no", "on" },
4392 { "ibrs-all", "on" },
4393 { "skip-l1dfl-vmentry", "on" },
4394 { "mds-no", "on" },
4395 { "pschange-mc-no", "on" },
4396 { "taa-no", "on" },
4403 { "sha-ni", "on" },
4407 { "vmx-rdseed-exit", "on" },
4408 { "vmx-pml", "on" },
4409 { "vmx-eptp-switching", "on" },
4419 { "vmx-xsaves", "on" },
4425 .note = "5-level EPT",
4427 { "vmx-page-walk-5", "on" },
4433 .note = "TSX, taa-no",
4435 /* Restore TSX features removed by -v2 above */
4573 { "sbdr-ssdp-no", "on" },
4574 { "fbsdp-no", "on" },
4575 { "psdp-no", "on" },
4583 { "tsc-adjust", "on" },
4730 { "tsc-adjust", "on" },
4735 { "avx10-128", "on" },
4736 { "avx10-256", "on" },
4737 { "avx10-512", "on" },
4738 { "avx10-version", "1" },
4873 { "tsc-adjust", "on" },
4877 { "gds-no", "on" },
4878 { "rfds-no", "on" },
4880 { "intel-psfd", "on"},
4881 { "ipred-ctrl", "on"},
4882 { "rrsba-ctrl", "on"},
4883 { "bhi-ctrl", "on"},
5129 { "vmx-xsaves", "on" },
5252 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
5261 { "vmx-xsaves", "on" },
5267 .note = "no split lock detect, no core-capability",
5269 { "split-lock-detect", "off" },
5270 { "core-capability", "off" },
5497 .alias = "EPYC-IBPB",
5500 { "model-id",
5509 { "perfctr-core", "on" },
5513 { "model-id",
5521 { "model-id",
5522 "AMD EPYC-v4 Processor" },
5530 { "overflow-recov", "on" },
5533 { "tsc-scale", "on" },
5534 { "vmcb-clean", "on" },
5536 { "pause-filter", "on" },
5538 { "v-vmsave-vmload", "on" },
5540 { "model-id",
5541 "AMD EPYC-v5 Processor" },
5607 .name = "EPYC-Rome",
5653 .model_id = "AMD EPYC-Rome Processor",
5661 { "amd-ssbd", "on" },
5668 { "model-id",
5669 "AMD EPYC-Rome-v3 Processor" },
5678 { "model-id",
5679 "AMD EPYC-Rome-v4 Processor (no XSAVES)" },
5687 { "overflow-recov", "on" },
5690 { "tsc-scale", "on" },
5691 { "vmcb-clean", "on" },
5693 { "pause-filter", "on" },
5695 { "v-vmsave-vmload", "on" },
5697 { "model-id",
5698 "AMD EPYC-Rome-v5 Processor" },
5707 .name = "EPYC-Milan",
5758 .model_id = "AMD EPYC-Milan Processor",
5765 { "model-id",
5766 "AMD EPYC-Milan-v2 Processor" },
5769 { "stibp-always-on", "on" },
5770 { "amd-psfd", "on" },
5771 { "no-nested-data-bp", "on" },
5772 { "lfence-always-serializing", "on" },
5773 { "null-sel-clr-base", "on" },
5781 { "overflow-recov", "on" },
5784 { "tsc-scale", "on" },
5785 { "vmcb-clean", "on" },
5787 { "pause-filter", "on" },
5789 { "v-vmsave-vmload", "on" },
5791 { "model-id",
5792 "AMD EPYC-Milan-v3 Processor" },
5801 .name = "EPYC-Genoa",
5869 .model_id = "AMD EPYC-Genoa Processor",
5876 { "overflow-recov", "on" },
5879 { "tsc-scale", "on" },
5880 { "vmcb-clean", "on" },
5882 { "pause-filter", "on" },
5884 { "v-vmsave-vmload", "on" },
5886 { "fs-gs-base-ns", "on" },
5887 { "perfmon-v2", "on" },
5888 { "model-id",
5889 "AMD EPYC-Genoa-v2 Processor" },
6034 .name = "EPYC-Turin",
6113 .model_id = "AMD EPYC-Turin Processor",
6119 * We resolve CPU model aliases using -v1 when using "-machine
6138 x86_cpu_def_get_versions(model->cpudef); in x86_cpu_model_last_version()
6139 while (vdef->version) { in x86_cpu_model_last_version()
6140 v = vdef->version; in x86_cpu_model_last_version()
6149 X86CPUVersion v = model->version; in x86_cpu_model_resolve_version()
6161 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
6169 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { in max_x86_cpu_realize()
6188 xcc->ordering = 9; in max_x86_cpu_class_init()
6190 xcc->model_description = in max_x86_cpu_class_init()
6194 dc->realize = max_x86_cpu_realize; in max_x86_cpu_class_init()
6204 cpu->max_features = true; in max_x86_cpu_initfn()
6213 object_property_set_str(OBJECT(cpu), "model-id", in max_x86_cpu_initfn()
6227 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); in feature_word_description()
6229 switch (f->type) { in feature_word_description()
6232 const char *reg = get_register_name_32(f->cpuid.reg); in feature_word_description()
6234 if (!f->cpuid.needs_ecx) { in feature_word_description()
6235 return g_strdup_printf("CPUID[eax=%02Xh].%s", f->cpuid.eax, reg); in feature_word_description()
6238 f->cpuid.eax, f->cpuid.ecx, reg); in feature_word_description()
6243 f->msr.index); in feature_word_description()
6254 if (cpu->filtered_features[w]) { in x86_cpu_have_filtered_features()
6265 CPUX86State *env = &cpu->env; in mark_unavailable_features()
6270 if (!cpu->force_features) { in mark_unavailable_features()
6271 env->features[w] &= ~mask; in mark_unavailable_features()
6273 cpu->filtered_features[w] |= mask; in mark_unavailable_features()
6284 f->feat_names[i] ? "." : "", in mark_unavailable_features()
6285 f->feat_names[i] ? f->feat_names[i] : "", i); in mark_unavailable_features()
6293 CPUX86State *env = &cpu->env; in mark_forced_on_features()
6297 if (!cpu->force_features) { in mark_forced_on_features()
6298 env->features[w] |= mask; in mark_forced_on_features()
6301 cpu->forced_on_features[w] |= mask; in mark_forced_on_features()
6313 f->feat_names[i] ? "." : "", in mark_forced_on_features()
6314 f->feat_names[i] ? f->feat_names[i] : "", i); in mark_forced_on_features()
6324 CPUX86State *env = &cpu->env; in x86_cpuid_version_get_family()
6327 value = (env->cpuid_version >> 8) & 0xf; in x86_cpuid_version_get_family()
6329 value += (env->cpuid_version >> 20) & 0xff; in x86_cpuid_version_get_family()
6339 CPUX86State *env = &cpu->env; in x86_cpuid_version_set_family()
6352 env->cpuid_version &= ~0xff00f00; in x86_cpuid_version_set_family()
6354 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); in x86_cpuid_version_set_family()
6356 env->cpuid_version |= value << 8; in x86_cpuid_version_set_family()
6365 CPUX86State *env = &cpu->env; in x86_cpuid_version_get_model()
6368 value = (env->cpuid_version >> 4) & 0xf; in x86_cpuid_version_get_model()
6369 value |= ((env->cpuid_version >> 16) & 0xf) << 4; in x86_cpuid_version_get_model()
6378 CPUX86State *env = &cpu->env; in x86_cpuid_version_set_model()
6391 env->cpuid_version &= ~0xf00f0; in x86_cpuid_version_set_model()
6392 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); in x86_cpuid_version_set_model()
6400 CPUX86State *env = &cpu->env; in x86_cpuid_version_get_stepping()
6403 value = env->cpuid_version & 0xf; in x86_cpuid_version_get_stepping()
6412 CPUX86State *env = &cpu->env; in x86_cpuid_version_set_stepping()
6425 env->cpuid_version &= ~0xf; in x86_cpuid_version_set_stepping()
6426 env->cpuid_version |= value & 0xf; in x86_cpuid_version_set_stepping()
6432 CPUX86State *env = &cpu->env; in x86_cpuid_get_vendor()
6436 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, in x86_cpuid_get_vendor()
6437 env->cpuid_vendor3); in x86_cpuid_get_vendor()
6445 CPUX86State *env = &cpu->env; in x86_cpuid_set_vendor()
6454 env->cpuid_vendor1 = 0; in x86_cpuid_set_vendor()
6455 env->cpuid_vendor2 = 0; in x86_cpuid_set_vendor()
6456 env->cpuid_vendor3 = 0; in x86_cpuid_set_vendor()
6458 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); in x86_cpuid_set_vendor()
6459 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); in x86_cpuid_set_vendor()
6460 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); in x86_cpuid_set_vendor()
6467 CPUX86State *env = &cpu->env; in x86_cpuid_get_model_id()
6473 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); in x86_cpuid_get_model_id()
6483 CPUX86State *env = &cpu->env; in x86_cpuid_set_model_id()
6490 memset(env->cpuid_model, 0, 48); in x86_cpuid_set_model_id()
6497 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); in x86_cpuid_set_model_id()
6507 value = cpu->env.tsc_khz * 1000; in x86_cpuid_get_tsc_freq()
6527 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; in x86_cpuid_set_tsc_freq()
6530 /* Generic getter for "feature-words" and "filtered-features" properties */
6544 * We didn't have MSR features when "feature-words" was in x86_cpu_get_feature_words()
6547 if (wi->type != CPUID_FEATURE_WORD) { in x86_cpu_get_feature_words()
6551 qwi->cpuid_input_eax = wi->cpuid.eax; in x86_cpu_get_feature_words()
6552 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; in x86_cpu_get_feature_words()
6553 qwi->cpuid_input_ecx = wi->cpuid.ecx; in x86_cpu_get_feature_words()
6554 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; in x86_cpu_get_feature_words()
6555 qwi->features = array[w]; in x86_cpu_get_feature_words()
6563 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); in x86_cpu_get_feature_words()
6566 /* Convert all '_' in a feature string option name to '-', to make feature
6567 * name conform to QOM property naming rule, which uses '-' instead of '_'.
6572 *s = '-'; in feat2prop()
6600 /* Compatibility hack to maintain legacy +-feat semantic,
6601 * where +-feat overwrites any feature set by
6602 * feat=on|feat even if the later is parsed after +-feat
6603 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
6612 /* Parse "+feature,-feature,feature=foo" CPU feature string
6644 } else if (featurestr[0] == '-') { in x86_cpu_parse_featurestr()
6669 "Don't mix both \"-%s\" and \"%s=%s\"", in x86_cpu_parse_featurestr()
6675 if (!strcmp(name, "tsc-freq")) { in x86_cpu_parse_featurestr()
6686 name = "tsc-frequency"; in x86_cpu_parse_featurestr()
6690 prop->driver = typename; in x86_cpu_parse_featurestr()
6691 prop->property = g_strdup(name); in x86_cpu_parse_featurestr()
6692 prop->value = g_strdup(val); in x86_cpu_parse_featurestr()
6729 x86_cpu_list_feature_names(xc->filtered_features, &result); in x86_cpu_get_unavailable_features()
6730 visit_type_strList(v, "unavailable-features", &result, errp); in x86_cpu_get_unavailable_features()
6740 for (tmp = features; tmp; tmp = tmp->next) { in listflags()
6741 const char *name = tmp->data; in listflags()
6761 if (cc_a->ordering != cc_b->ordering) { in x86_cpu_list_compare()
6762 ret = cc_a->ordering - cc_b->ordering; in x86_cpu_list_compare()
6781 char *r = object_property_get_str(obj, "model-id", &error_abort); in x86_cpu_class_get_model_id()
6790 if (!cc->model || !cc->model->is_alias) { in x86_cpu_class_get_alias_of()
6793 version = x86_cpu_model_resolve_version(cc->model); in x86_cpu_class_get_alias_of()
6797 return x86_cpu_versioned_model_name(cc->model->cpudef, version); in x86_cpu_class_get_alias_of()
6805 g_autofree char *desc = g_strdup(cc->model_description); in x86_cpu_list_entry()
6810 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { in x86_cpu_list_entry()
6816 if (!desc && cc->model && cc->model->note) { in x86_cpu_list_entry()
6817 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); in x86_cpu_list_entry()
6823 if (cc->model && cc->model->cpudef->deprecation_note) { in x86_cpu_list_entry()
6828 qemu_printf(" %-20s %s\n", name, desc); in x86_cpu_list_entry()
6852 if (fw->feat_names[j]) { in x86_cpu_list()
6853 names = g_list_append(names, (gpointer)fw->feat_names[j]); in x86_cpu_list()
6878 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { in x86_cpu_class_check_missing_features()
6897 x86_cpu_list_feature_names(xc->filtered_features, tail); in x86_cpu_class_check_missing_features()
6910 info->name = x86_cpu_class_get_model_name(cc); in x86_cpu_definition_entry()
6911 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); in x86_cpu_definition_entry()
6912 info->has_unavailable_features = true; in x86_cpu_definition_entry()
6913 info->q_typename = g_strdup(object_class_get_name(oc)); in x86_cpu_definition_entry()
6914 info->migration_safe = cc->migration_safe; in x86_cpu_definition_entry()
6915 info->has_migration_safe = true; in x86_cpu_definition_entry()
6916 info->q_static = cc->static_model; in x86_cpu_definition_entry()
6917 if (cc->model && cc->model->cpudef->deprecation_note) { in x86_cpu_definition_entry()
6918 info->deprecated = true; in x86_cpu_definition_entry()
6920 info->deprecated = false; in x86_cpu_definition_entry()
6927 info->alias_of = x86_cpu_class_get_alias_of(cc); in x86_cpu_definition_entry()
6951 switch (wi->type) { in x86_cpu_get_supported_feature_word()
6953 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, in x86_cpu_get_supported_feature_word()
6954 wi->cpuid.ecx, in x86_cpu_get_supported_feature_word()
6955 wi->cpuid.reg); in x86_cpu_get_supported_feature_word()
6959 wi->msr.index); in x86_cpu_get_supported_feature_word()
6963 if (wi->type != CPUID_FEATURE_WORD) { in x86_cpu_get_supported_feature_word()
6966 r = hvf_get_supported_cpuid(wi->cpuid.eax, in x86_cpu_get_supported_feature_word()
6967 wi->cpuid.ecx, in x86_cpu_get_supported_feature_word()
6968 wi->cpuid.reg); in x86_cpu_get_supported_feature_word()
6970 r = wi->tcg_features; in x86_cpu_get_supported_feature_word()
6979 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no in x86_cpu_get_supported_feature_word()
6980 * way for userspace to get out of its 32-bit jail, we can leave in x86_cpu_get_supported_feature_word()
6990 if (cpu && !IS_AMD_CPU(&cpu->env)) { in x86_cpu_get_supported_feature_word()
7016 if (cpu && cpu->migratable) { in x86_cpu_get_supported_feature_word()
7081 for (pv = props; pv->prop; pv++) { in x86_cpu_apply_props()
7082 if (!pv->value) { in x86_cpu_apply_props()
7085 object_property_parse(OBJECT(cpu), pv->prop, pv->value, in x86_cpu_apply_props()
7104 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { in x86_cpu_apply_version_props()
7107 for (p = vdef->props; p && p->prop; p++) { in x86_cpu_apply_version_props()
7108 object_property_parse(OBJECT(cpu), p->prop, p->value, in x86_cpu_apply_version_props()
7112 if (vdef->version == version) { in x86_cpu_apply_version_props()
7120 assert(vdef->version == version); in x86_cpu_apply_version_props()
7128 const CPUCaches *cache_info = model->cpudef->cache_info; in x86_cpu_get_versioned_cache_info()
7134 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { in x86_cpu_get_versioned_cache_info()
7135 if (vdef->cache_info) { in x86_cpu_get_versioned_cache_info()
7136 cache_info = vdef->cache_info; in x86_cpu_get_versioned_cache_info()
7139 if (vdef->version == version) { in x86_cpu_get_versioned_cache_info()
7144 assert(vdef->version == version); in x86_cpu_get_versioned_cache_info()
7154 const X86CPUDefinition *def = model->cpudef; in x86_cpu_load_model()
7155 CPUX86State *env = &cpu->env; in x86_cpu_load_model()
7160 * query-cpu-model-expansion is always complete. in x86_cpu_load_model()
7164 object_property_set_uint(OBJECT(cpu), "min-level", def->level, in x86_cpu_load_model()
7166 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, in x86_cpu_load_model()
7169 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); in x86_cpu_load_model()
7170 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); in x86_cpu_load_model()
7171 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, in x86_cpu_load_model()
7173 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, in x86_cpu_load_model()
7176 env->features[w] = def->features[w]; in x86_cpu_load_model()
7179 /* legacy-cache defaults to 'off' if CPU model provides cache info */ in x86_cpu_load_model()
7180 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); in x86_cpu_load_model()
7182 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; in x86_cpu_load_model()
7189 * when doing cross vendor migration in x86_cpu_load_model()
7196 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); in x86_cpu_load_model()
7198 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, in x86_cpu_load_model()
7205 * We can simply clear env->user_features here since it will be filled later in x86_cpu_load_model()
7208 memset(&env->user_features, 0, sizeof(env->user_features)); in x86_cpu_load_model()
7214 return "i386:x86-64"; in x86_gdb_arch_name()
7216 return "i386"; in x86_gdb_arch_name()
7226 xcc->model = model; in x86_cpu_cpudef_class_init()
7227 xcc->migration_safe = true; in x86_cpu_cpudef_class_init()
7228 cc->deprecation_note = model->cpudef->deprecation_note; in x86_cpu_cpudef_class_init()
7258 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); in x86_register_cpudef_types()
7260 assert(def->model_id && strlen(def->model_id) <= 48); in x86_register_cpudef_types()
7264 m->cpudef = def; in x86_register_cpudef_types()
7265 m->version = CPU_VERSION_AUTO; in x86_register_cpudef_types()
7266 m->is_alias = true; in x86_register_cpudef_types()
7267 x86_register_cpu_model_type(def->name, m); in x86_register_cpudef_types()
7271 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { in x86_register_cpudef_types()
7273 x86_cpu_versioned_model_name(def, vdef->version); in x86_register_cpudef_types()
7276 m->cpudef = def; in x86_register_cpudef_types()
7277 m->version = vdef->version; in x86_register_cpudef_types()
7278 m->note = vdef->note; in x86_register_cpudef_types()
7281 if (vdef->alias) { in x86_register_cpudef_types()
7283 am->cpudef = def; in x86_register_cpudef_types()
7284 am->version = vdef->version; in x86_register_cpudef_types()
7285 am->is_alias = true; in x86_register_cpudef_types()
7286 x86_register_cpu_model_type(vdef->alias, am); in x86_register_cpudef_types()
7294 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { in cpu_x86_virtual_addr_width()
7309 X86CPUTopoInfo *topo_info = &env->topo_info; in cpu_x86_cpuid()
7316 limit = env->cpuid_xlevel2; in cpu_x86_cpuid()
7318 limit = env->cpuid_xlevel; in cpu_x86_cpuid()
7322 limit = env->cpuid_level; in cpu_x86_cpuid()
7328 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) in cpu_x86_cpuid()
7330 index = env->cpuid_level; in cpu_x86_cpuid()
7335 *eax = env->cpuid_level; in cpu_x86_cpuid()
7336 *ebx = env->cpuid_vendor1; in cpu_x86_cpuid()
7337 *edx = env->cpuid_vendor2; in cpu_x86_cpuid()
7338 *ecx = env->cpuid_vendor3; in cpu_x86_cpuid()
7341 *eax = env->cpuid_version; in cpu_x86_cpuid()
7342 *ebx = (cpu->apic_id << 24) | in cpu_x86_cpuid()
7344 *ecx = env->features[FEAT_1_ECX]; in cpu_x86_cpuid()
7345 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { in cpu_x86_cpuid()
7348 *edx = env->features[FEAT_1_EDX]; in cpu_x86_cpuid()
7352 if (!cpu->enable_pmu) { in cpu_x86_cpuid()
7358 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
7361 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { in cpu_x86_cpuid()
7367 if (!cpu->enable_l3_cache) { in cpu_x86_cpuid()
7370 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); in cpu_x86_cpuid()
7372 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | in cpu_x86_cpuid()
7373 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | in cpu_x86_cpuid()
7374 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); in cpu_x86_cpuid()
7378 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
7397 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { in cpu_x86_cpuid()
7404 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, in cpu_x86_cpuid()
7407 if (!cpu->l1_cache_per_core) { in cpu_x86_cpuid()
7412 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, in cpu_x86_cpuid()
7415 if (!cpu->l1_cache_per_core) { in cpu_x86_cpuid()
7420 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, in cpu_x86_cpuid()
7425 if (cpu->enable_l3_cache) { in cpu_x86_cpuid()
7426 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, in cpu_x86_cpuid()
7440 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ in cpu_x86_cpuid()
7441 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ in cpu_x86_cpuid()
7442 *ecx = cpu->mwait.ecx; /* flags */ in cpu_x86_cpuid()
7443 *edx = cpu->mwait.edx; /* mwait substates */ in cpu_x86_cpuid()
7447 *eax = env->features[FEAT_6_EAX]; in cpu_x86_cpuid()
7455 /* Maximum ECX value for sub-leaves */ in cpu_x86_cpuid()
7456 *eax = env->cpuid_level_func7; in cpu_x86_cpuid()
7457 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ in cpu_x86_cpuid()
7458 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ in cpu_x86_cpuid()
7459 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { in cpu_x86_cpuid()
7462 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ in cpu_x86_cpuid()
7464 *eax = env->features[FEAT_7_1_EAX]; in cpu_x86_cpuid()
7465 *ecx = env->features[FEAT_7_1_ECX]; in cpu_x86_cpuid()
7466 *edx = env->features[FEAT_7_1_EDX]; in cpu_x86_cpuid()
7469 *edx = env->features[FEAT_7_2_EDX]; in cpu_x86_cpuid()
7482 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ in cpu_x86_cpuid()
7489 if (cpu->enable_pmu) { in cpu_x86_cpuid()
7500 if (!cpu->enable_cpuid_0xb) { in cpu_x86_cpuid()
7506 *edx = cpu->apic_id; in cpu_x86_cpuid()
7511 *ebx = topo_info->threads_per_core; in cpu_x86_cpuid()
7529 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { in cpu_x86_cpuid()
7549 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { in cpu_x86_cpuid()
7555 *eax = env->features[FEAT_XSAVE_XCR0_LO]; in cpu_x86_cpuid()
7556 *edx = env->features[FEAT_XSAVE_XCR0_HI]; in cpu_x86_cpuid()
7563 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); in cpu_x86_cpuid()
7568 *eax = env->features[FEAT_XSAVE]; in cpu_x86_cpuid()
7570 *ecx = env->features[FEAT_XSAVE_XSS_LO]; in cpu_x86_cpuid()
7571 *edx = env->features[FEAT_XSAVE_XSS_HI]; in cpu_x86_cpuid()
7572 if (kvm_enabled() && cpu->enable_pmu && in cpu_x86_cpuid()
7573 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && in cpu_x86_cpuid()
7579 } else if (count == 0xf && cpu->enable_pmu in cpu_x86_cpuid()
7580 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { in cpu_x86_cpuid()
7586 *eax = esa->size; in cpu_x86_cpuid()
7587 *ebx = esa->offset; in cpu_x86_cpuid()
7588 *ecx = esa->ecx & in cpu_x86_cpuid()
7591 *eax = esa->size; in cpu_x86_cpuid()
7601 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { in cpu_x86_cpuid()
7607 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve in cpu_x86_cpuid()
7615 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { in cpu_x86_cpuid()
7628 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware in cpu_x86_cpuid()
7636 *eax &= env->features[FEAT_SGX_12_0_EAX]; in cpu_x86_cpuid()
7637 *ebx &= env->features[FEAT_SGX_12_0_EBX]; in cpu_x86_cpuid()
7639 *eax &= env->features[FEAT_SGX_12_1_EAX]; in cpu_x86_cpuid()
7641 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; in cpu_x86_cpuid()
7642 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; in cpu_x86_cpuid()
7649 !kvm_enable_sgx_provisioning(cs->kvm_state)) { in cpu_x86_cpuid()
7661 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || in cpu_x86_cpuid()
7674 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { in cpu_x86_cpuid()
7689 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { in cpu_x86_cpuid()
7710 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { in cpu_x86_cpuid()
7725 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { in cpu_x86_cpuid()
7726 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; in cpu_x86_cpuid()
7735 if (tcg_enabled() && cpu->expose_tcg) { in cpu_x86_cpuid()
7755 *eax = env->cpuid_xlevel; in cpu_x86_cpuid()
7756 *ebx = env->cpuid_vendor1; in cpu_x86_cpuid()
7757 *edx = env->cpuid_vendor2; in cpu_x86_cpuid()
7758 *ecx = env->cpuid_vendor3; in cpu_x86_cpuid()
7761 *eax = env->cpuid_version; in cpu_x86_cpuid()
7763 *ecx = env->features[FEAT_8000_0001_ECX]; in cpu_x86_cpuid()
7764 *edx = env->features[FEAT_8000_0001_EDX]; in cpu_x86_cpuid()
7766 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && in cpu_x86_cpuid()
7767 !(env->hflags & HF_LMA_MASK)) { in cpu_x86_cpuid()
7774 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; in cpu_x86_cpuid()
7775 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; in cpu_x86_cpuid()
7776 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; in cpu_x86_cpuid()
7777 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; in cpu_x86_cpuid()
7781 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
7789 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); in cpu_x86_cpuid()
7790 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); in cpu_x86_cpuid()
7794 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
7806 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, in cpu_x86_cpuid()
7807 cpu->enable_l3_cache ? in cpu_x86_cpuid()
7808 env->cache_info_amd.l3_cache : NULL, in cpu_x86_cpuid()
7813 *ebx = env->features[FEAT_8000_0007_EBX]; in cpu_x86_cpuid()
7815 *edx = env->features[FEAT_8000_0007_EDX]; in cpu_x86_cpuid()
7819 *eax = cpu->phys_bits; in cpu_x86_cpuid()
7820 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { in cpu_x86_cpuid()
7823 *eax |= (cpu->guest_phys_bits << 16); in cpu_x86_cpuid()
7825 *ebx = env->features[FEAT_8000_0008_EBX]; in cpu_x86_cpuid()
7834 (threads_per_pkg - 1); in cpu_x86_cpuid()
7841 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { in cpu_x86_cpuid()
7845 *edx = env->features[FEAT_SVM]; /* optional features */ in cpu_x86_cpuid()
7855 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
7861 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, in cpu_x86_cpuid()
7865 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, in cpu_x86_cpuid()
7869 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, in cpu_x86_cpuid()
7873 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, in cpu_x86_cpuid()
7880 if (cpu->amd_topoext_features_only) { in cpu_x86_cpuid()
7885 if (cpu->core_id <= 255) { in cpu_x86_cpuid()
7897 if (kvm_enabled() && cpu->enable_pmu && in cpu_x86_cpuid()
7898 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { in cpu_x86_cpuid()
7900 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, in cpu_x86_cpuid()
7905 *eax = env->cpuid_xlevel2; in cpu_x86_cpuid()
7912 *eax = env->cpuid_version; in cpu_x86_cpuid()
7915 *edx = env->features[FEAT_C000_0001_EDX]; in cpu_x86_cpuid()
7938 *eax = env->features[FEAT_8000_0021_EAX]; in cpu_x86_cpuid()
7939 *ebx = env->features[FEAT_8000_0021_EBX]; in cpu_x86_cpuid()
7955 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; in x86_cpu_set_sgxlepubkeyhash()
7956 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; in x86_cpu_set_sgxlepubkeyhash()
7957 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; in x86_cpu_set_sgxlepubkeyhash()
7958 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; in x86_cpu_set_sgxlepubkeyhash()
7964 if (!esa->size) { in cpuid_has_xsave_feature()
7968 if (env->features[esa->feature] & esa->bits) { in cpuid_has_xsave_feature()
7971 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F in cpuid_has_xsave_feature()
7972 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { in cpuid_has_xsave_feature()
7984 CPUX86State *env = &cpu->env; in x86_cpu_reset_hold()
7989 if (xcc->parent_phases.hold) { in x86_cpu_reset_hold()
7990 xcc->parent_phases.hold(obj, type); in x86_cpu_reset_hold()
7999 env->old_exception = -1; in x86_cpu_reset_hold()
8002 env->int_ctl = 0; in x86_cpu_reset_hold()
8003 env->hflags2 |= HF2_GIF_MASK; in x86_cpu_reset_hold()
8004 env->hflags2 |= HF2_VGIF_MASK; in x86_cpu_reset_hold()
8005 env->hflags &= ~HF_GUEST_MASK; in x86_cpu_reset_hold()
8008 env->a20_mask = ~0x0; in x86_cpu_reset_hold()
8009 env->smbase = 0x30000; in x86_cpu_reset_hold()
8010 env->msr_smi_count = 0; in x86_cpu_reset_hold()
8012 env->idt.limit = 0xffff; in x86_cpu_reset_hold()
8013 env->gdt.limit = 0xffff; in x86_cpu_reset_hold()
8014 env->ldt.limit = 0xffff; in x86_cpu_reset_hold()
8015 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); in x86_cpu_reset_hold()
8016 env->tr.limit = 0xffff; in x86_cpu_reset_hold()
8017 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); in x86_cpu_reset_hold()
8038 env->eip = 0xfff0; in x86_cpu_reset_hold()
8039 env->regs[R_EDX] = env->cpuid_version; in x86_cpu_reset_hold()
8041 env->eflags = 0x2; in x86_cpu_reset_hold()
8045 env->fptags[i] = 1; in x86_cpu_reset_hold()
8049 env->mxcsr = 0x1f80; in x86_cpu_reset_hold()
8051 env->xstate_bv = 0; in x86_cpu_reset_hold()
8053 env->pat = 0x0007040600070406ULL; in x86_cpu_reset_hold()
8057 * KVM handles TSC = 0 specially and thinks we are hot-plugging in x86_cpu_reset_hold()
8060 if (env->tsc != 0) { in x86_cpu_reset_hold()
8061 env->tsc = 1; in x86_cpu_reset_hold()
8064 env->tsc = 0; in x86_cpu_reset_hold()
8067 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; in x86_cpu_reset_hold()
8068 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { in x86_cpu_reset_hold()
8069 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; in x86_cpu_reset_hold()
8072 memset(env->dr, 0, sizeof(env->dr)); in x86_cpu_reset_hold()
8073 env->dr[6] = DR6_FIXED_1; in x86_cpu_reset_hold()
8074 env->dr[7] = DR7_FIXED_1; in x86_cpu_reset_hold()
8082 /* Enable all the features for user-mode. */ in x86_cpu_reset_hold()
8083 if (env->features[FEAT_1_EDX] & CPUID_SSE) { in x86_cpu_reset_hold()
8096 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { in x86_cpu_reset_hold()
8099 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { in x86_cpu_reset_hold()
8104 env->xcr0 = xcr0; in x86_cpu_reset_hold()
8109 * - IA32_MTRR_DEF_TYPE MSR.E = 0 in x86_cpu_reset_hold()
8110 * - IA32_MTRR_PHYSMASKn.V = 0 in x86_cpu_reset_hold()
8113 env->mtrr_deftype = 0; in x86_cpu_reset_hold()
8114 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); in x86_cpu_reset_hold()
8115 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); in x86_cpu_reset_hold()
8117 env->interrupt_injected = -1; in x86_cpu_reset_hold()
8118 env->exception_nr = -1; in x86_cpu_reset_hold()
8119 env->exception_pending = 0; in x86_cpu_reset_hold()
8120 env->exception_injected = 0; in x86_cpu_reset_hold()
8121 env->exception_has_payload = false; in x86_cpu_reset_hold()
8122 env->exception_payload = 0; in x86_cpu_reset_hold()
8123 env->nmi_injected = false; in x86_cpu_reset_hold()
8124 env->triple_fault_pending = false; in x86_cpu_reset_hold()
8126 /* We hard-wire the BSP to the first CPU. */ in x86_cpu_reset_hold()
8127 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); in x86_cpu_reset_hold()
8129 cs->halted = !cpu_is_bsp(cpu); in x86_cpu_reset_hold()
8137 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; in x86_cpu_reset_hold()
8149 if (cpu->apic_state) { in x86_cpu_after_reset()
8150 device_cold_reset(cpu->apic_state); in x86_cpu_after_reset()
8157 CPUX86State *cenv = &cpu->env; in mce_init()
8160 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 in mce_init()
8161 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == in mce_init()
8163 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | in mce_init()
8164 (cpu->enable_lmce ? MCG_LMCE_P : 0); in mce_init()
8165 cenv->mcg_ctl = ~(uint64_t)0; in mce_init()
8167 cenv->mce_banks[bank * 4] = ~(uint64_t)0; in mce_init()
8182 CPUX86State *env = &cpu->env; in x86_cpu_adjust_feat_level()
8184 uint32_t eax = fi->cpuid.eax; in x86_cpu_adjust_feat_level()
8188 if (!env->features[w]) { in x86_cpu_adjust_feat_level()
8194 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); in x86_cpu_adjust_feat_level()
8197 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); in x86_cpu_adjust_feat_level()
8200 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); in x86_cpu_adjust_feat_level()
8205 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, in x86_cpu_adjust_feat_level()
8206 fi->cpuid.ecx); in x86_cpu_adjust_feat_level()
8213 CPUX86State *env = &cpu->env; in x86_cpu_enable_xsave_components()
8218 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { in x86_cpu_enable_xsave_components()
8219 env->features[FEAT_XSAVE_XCR0_LO] = 0; in x86_cpu_enable_xsave_components()
8220 env->features[FEAT_XSAVE_XCR0_HI] = 0; in x86_cpu_enable_xsave_components()
8221 env->features[FEAT_XSAVE_XSS_LO] = 0; in x86_cpu_enable_xsave_components()
8222 env->features[FEAT_XSAVE_XSS_HI] = 0; in x86_cpu_enable_xsave_components()
8240 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; in x86_cpu_enable_xsave_components()
8241 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; in x86_cpu_enable_xsave_components()
8242 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; in x86_cpu_enable_xsave_components()
8243 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; in x86_cpu_enable_xsave_components()
8270 * - CPU instance creation (instance_init) will run only CPU
8271 * model loading. CPU expansion can't run at instance_init-time
8273 * - CPU realization will perform both CPU model expansion and CPUID
8275 * - query-cpu-definitions needs to run all 3 steps. It needs
8276 * to run CPUID filtering, as the 'unavailable-features'
8278 * - The query-cpu-model-expansion QMP command only needs to run
8288 CPUX86State *env = &cpu->env; in x86_cpu_expand_features()
8293 for (l = plus_features; l; l = l->next) { in x86_cpu_expand_features()
8294 const char *prop = l->data; in x86_cpu_expand_features()
8300 for (l = minus_features; l; l = l->next) { in x86_cpu_expand_features()
8301 const char *prop = l->data; in x86_cpu_expand_features()
8307 /*TODO: Now cpu->max_features doesn't overwrite features in x86_cpu_expand_features()
8312 if (cpu->max_features) { in x86_cpu_expand_features()
8317 env->features[w] |= in x86_cpu_expand_features()
8319 ~env->user_features[w] & in x86_cpu_expand_features()
8323 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { in x86_cpu_expand_features()
8326 env->avx10_version = ebx & 0xff; in x86_cpu_expand_features()
8330 if (x86_threads_per_pkg(&env->topo_info) > 1) { in x86_cpu_expand_features()
8331 env->features[FEAT_1_EDX] |= CPUID_HT; in x86_cpu_expand_features()
8340 env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; in x86_cpu_expand_features()
8346 if (!(env->features[d->from.index] & d->from.mask)) { in x86_cpu_expand_features()
8347 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; in x86_cpu_expand_features()
8350 mark_unavailable_features(cpu, d->to.index, in x86_cpu_expand_features()
8351 unavailable_features & env->user_features[d->to.index], in x86_cpu_expand_features()
8354 env->features[d->to.index] &= ~unavailable_features; in x86_cpu_expand_features()
8358 if (!kvm_enabled() || !cpu->expose_kvm) { in x86_cpu_expand_features()
8359 env->features[FEAT_KVM] = 0; in x86_cpu_expand_features()
8366 if (cpu->full_cpuid_auto_level) { in x86_cpu_expand_features()
8384 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { in x86_cpu_expand_features()
8385 if (cpu->intel_pt_auto_level) { in x86_cpu_expand_features()
8386 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); in x86_cpu_expand_features()
8387 } else if (cpu->env.cpuid_min_level < 0x14) { in x86_cpu_expand_features()
8390 … "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); in x86_cpu_expand_features()
8395 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. in x86_cpu_expand_features()
8398 * cpu->vendor_cpuid_only has been unset for compatibility with older in x86_cpu_expand_features()
8402 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { in x86_cpu_expand_features()
8403 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); in x86_cpu_expand_features()
8407 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { in x86_cpu_expand_features()
8408 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); in x86_cpu_expand_features()
8412 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { in x86_cpu_expand_features()
8413 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); in x86_cpu_expand_features()
8418 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); in x86_cpu_expand_features()
8421 if (env->features[FEAT_8000_0021_EAX]) { in x86_cpu_expand_features()
8422 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); in x86_cpu_expand_features()
8426 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { in x86_cpu_expand_features()
8427 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); in x86_cpu_expand_features()
8432 if (env->cpuid_level_func7 == UINT32_MAX) { in x86_cpu_expand_features()
8433 env->cpuid_level_func7 = env->cpuid_min_level_func7; in x86_cpu_expand_features()
8435 if (env->cpuid_level == UINT32_MAX) { in x86_cpu_expand_features()
8436 env->cpuid_level = env->cpuid_min_level; in x86_cpu_expand_features()
8438 if (env->cpuid_xlevel == UINT32_MAX) { in x86_cpu_expand_features()
8439 env->cpuid_xlevel = env->cpuid_min_xlevel; in x86_cpu_expand_features()
8441 if (env->cpuid_xlevel2 == UINT32_MAX) { in x86_cpu_expand_features()
8442 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; in x86_cpu_expand_features()
8458 CPUX86State *env = &cpu->env; in x86_cpu_filter_features()
8475 uint64_t requested_features = env->features[w]; in x86_cpu_filter_features()
8484 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && in x86_cpu_filter_features()
8500 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { in x86_cpu_filter_features()
8504 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. in x86_cpu_filter_features()
8512 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { in x86_cpu_filter_features()
8517 if (version < env->avx10_version) { in x86_cpu_filter_features()
8520 prefix, env->avx10_version, version); in x86_cpu_filter_features()
8522 env->avx10_version = version; in x86_cpu_filter_features()
8525 } else if (env->avx10_version) { in x86_cpu_filter_features()
8527 warn_report("%s: avx10.%d.", prefix, env->avx10_version); in x86_cpu_filter_features()
8539 /* Hyper-V vendor id */ in x86_cpu_hyperv_realize()
8540 if (!cpu->hyperv_vendor) { in x86_cpu_hyperv_realize()
8541 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", in x86_cpu_hyperv_realize()
8544 len = strlen(cpu->hyperv_vendor); in x86_cpu_hyperv_realize()
8546 warn_report("hv-vendor-id truncated to 12 characters"); in x86_cpu_hyperv_realize()
8549 memset(cpu->hyperv_vendor_id, 0, 12); in x86_cpu_hyperv_realize()
8550 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); in x86_cpu_hyperv_realize()
8553 cpu->hyperv_interface_id[0] = 0x31237648; in x86_cpu_hyperv_realize()
8554 cpu->hyperv_interface_id[1] = 0; in x86_cpu_hyperv_realize()
8555 cpu->hyperv_interface_id[2] = 0; in x86_cpu_hyperv_realize()
8556 cpu->hyperv_interface_id[3] = 0; in x86_cpu_hyperv_realize()
8559 cpu->hyperv_limits[0] = 64; in x86_cpu_hyperv_realize()
8560 cpu->hyperv_limits[1] = 0; in x86_cpu_hyperv_realize()
8561 cpu->hyperv_limits[2] = 0; in x86_cpu_hyperv_realize()
8568 CPUX86State *env = &cpu->env; in x86_cpu_update_smp_cache_topo()
8573 env->cache_info_cpuid4.l1d_cache->share_level = level; in x86_cpu_update_smp_cache_topo()
8574 env->cache_info_amd.l1d_cache->share_level = level; in x86_cpu_update_smp_cache_topo()
8577 env->cache_info_cpuid4.l1d_cache->share_level); in x86_cpu_update_smp_cache_topo()
8579 env->cache_info_amd.l1d_cache->share_level); in x86_cpu_update_smp_cache_topo()
8584 env->cache_info_cpuid4.l1i_cache->share_level = level; in x86_cpu_update_smp_cache_topo()
8585 env->cache_info_amd.l1i_cache->share_level = level; in x86_cpu_update_smp_cache_topo()
8588 env->cache_info_cpuid4.l1i_cache->share_level); in x86_cpu_update_smp_cache_topo()
8590 env->cache_info_amd.l1i_cache->share_level); in x86_cpu_update_smp_cache_topo()
8595 env->cache_info_cpuid4.l2_cache->share_level = level; in x86_cpu_update_smp_cache_topo()
8596 env->cache_info_amd.l2_cache->share_level = level; in x86_cpu_update_smp_cache_topo()
8599 env->cache_info_cpuid4.l2_cache->share_level); in x86_cpu_update_smp_cache_topo()
8601 env->cache_info_amd.l2_cache->share_level); in x86_cpu_update_smp_cache_topo()
8606 env->cache_info_cpuid4.l3_cache->share_level = level; in x86_cpu_update_smp_cache_topo()
8607 env->cache_info_amd.l3_cache->share_level = level; in x86_cpu_update_smp_cache_topo()
8610 env->cache_info_cpuid4.l3_cache->share_level); in x86_cpu_update_smp_cache_topo()
8612 env->cache_info_amd.l3_cache->share_level); in x86_cpu_update_smp_cache_topo()
8627 CPUX86State *env = &cpu->env; in x86_cpu_realizefn()
8632 /* Use pc-relative instructions in system-mode */ in x86_cpu_realizefn()
8636 if (cpu->apic_id == UNASSIGNED_APIC_ID) { in x86_cpu_realizefn()
8637 error_setg(errp, "apic-id property was not initialized properly"); in x86_cpu_realizefn()
8642 * Process Hyper-V enlightenments. in x86_cpu_realizefn()
8653 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT in x86_cpu_realizefn()
8654 * with user-provided setting. in x86_cpu_realizefn()
8656 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { in x86_cpu_realizefn()
8657 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { in x86_cpu_realizefn()
8658 error_setg(errp, "invalid lbr-fmt"); in x86_cpu_realizefn()
8661 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; in x86_cpu_realizefn()
8662 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; in x86_cpu_realizefn()
8670 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; in x86_cpu_realizefn()
8676 if (!cpu->enable_pmu) { in x86_cpu_realizefn()
8681 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " in x86_cpu_realizefn()
8688 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { in x86_cpu_realizefn()
8689 if (cpu->enforce_cpuid) { in x86_cpu_realizefn()
8702 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; in x86_cpu_realizefn()
8703 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] in x86_cpu_realizefn()
8712 * These may be set by the accel-specific code, in x86_cpu_realizefn()
8721 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { in x86_cpu_realizefn()
8727 if (cpu->guest_phys_bits == -1) { in x86_cpu_realizefn()
8732 cpu->guest_phys_bits = 0; in x86_cpu_realizefn()
8735 if (cpu->ucode_rev == 0) { in x86_cpu_realizefn()
8739 * accel-specific code in cpu_exec_realizefn. in x86_cpu_realizefn()
8742 cpu->ucode_rev = 0x01000065; in x86_cpu_realizefn()
8744 cpu->ucode_rev = 0x100000000ULL; in x86_cpu_realizefn()
8752 * requires the accel-specific code in cpu_exec_realizefn to in x86_cpu_realizefn()
8753 * have already acquired the CPUID data into cpu->mwait. in x86_cpu_realizefn()
8755 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; in x86_cpu_realizefn()
8764 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && in x86_cpu_realizefn()
8765 env->topo_info.threads_per_core > 1) { in x86_cpu_realizefn()
8767 "hyperthreading(%d). Please configure -smp " in x86_cpu_realizefn()
8769 "feature.", env->topo_info.threads_per_core); in x86_cpu_realizefn()
8781 * accel-specific code in cpu_exec_realizefn. in x86_cpu_realizefn()
8783 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { in x86_cpu_realizefn()
8784 if (cpu->phys_bits && in x86_cpu_realizefn()
8785 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || in x86_cpu_realizefn()
8786 cpu->phys_bits < 32)) { in x86_cpu_realizefn()
8787 error_setg(errp, "phys-bits should be between 32 and %u " in x86_cpu_realizefn()
8789 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); in x86_cpu_realizefn()
8794 * compat_props or by the host code in host-cpu.c). in x86_cpu_realizefn()
8797 if (cpu->phys_bits == 0) { in x86_cpu_realizefn()
8798 cpu->phys_bits = TCG_PHYS_ADDR_BITS; in x86_cpu_realizefn()
8800 if (cpu->guest_phys_bits && in x86_cpu_realizefn()
8801 (cpu->guest_phys_bits > cpu->phys_bits || in x86_cpu_realizefn()
8802 cpu->guest_phys_bits < 32)) { in x86_cpu_realizefn()
8803 error_setg(errp, "guest-phys-bits should be between 32 and %u " in x86_cpu_realizefn()
8805 cpu->phys_bits, cpu->guest_phys_bits); in x86_cpu_realizefn()
8812 if (cpu->phys_bits != 0) { in x86_cpu_realizefn()
8813 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); in x86_cpu_realizefn()
8816 if (cpu->guest_phys_bits != 0) { in x86_cpu_realizefn()
8817 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); in x86_cpu_realizefn()
8821 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { in x86_cpu_realizefn()
8822 cpu->phys_bits = 36; in x86_cpu_realizefn()
8824 cpu->phys_bits = 32; in x86_cpu_realizefn()
8829 if (!cpu->legacy_cache) { in x86_cpu_realizefn()
8831 x86_cpu_get_versioned_cache_info(cpu, xcc->model); in x86_cpu_realizefn()
8833 if (!xcc->model || !cache_info) { in x86_cpu_realizefn()
8836 "CPU model '%s' doesn't support legacy-cache=off", name); in x86_cpu_realizefn()
8839 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = in x86_cpu_realizefn()
8843 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; in x86_cpu_realizefn()
8844 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; in x86_cpu_realizefn()
8845 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; in x86_cpu_realizefn()
8846 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; in x86_cpu_realizefn()
8848 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; in x86_cpu_realizefn()
8849 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; in x86_cpu_realizefn()
8850 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; in x86_cpu_realizefn()
8851 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; in x86_cpu_realizefn()
8853 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; in x86_cpu_realizefn()
8854 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; in x86_cpu_realizefn()
8855 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; in x86_cpu_realizefn()
8856 env->cache_info_amd.l3_cache = &legacy_l3_cache; in x86_cpu_realizefn()
8863 if (mc->smp_props.has_caches) { in x86_cpu_realizefn()
8871 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { in x86_cpu_realizefn()
8892 xcc->parent_realize(dev, &local_err); in x86_cpu_realizefn()
8911 if (cpu->apic_state) { in x86_cpu_unrealizefn()
8912 object_unparent(OBJECT(cpu->apic_state)); in x86_cpu_unrealizefn()
8913 cpu->apic_state = NULL; in x86_cpu_unrealizefn()
8916 xcc->parent_unrealize(dev); in x86_cpu_unrealizefn()
8929 uint64_t f = cpu->env.features[fp->w]; in x86_cpu_get_bit_prop()
8930 bool value = (f & fp->mask) == fp->mask; in x86_cpu_get_bit_prop()
8942 if (dev->realized) { in x86_cpu_set_bit_prop()
8952 cpu->env.features[fp->w] |= fp->mask; in x86_cpu_set_bit_prop()
8954 cpu->env.features[fp->w] &= ~fp->mask; in x86_cpu_set_bit_prop()
8956 cpu->env.user_features[fp->w] |= fp->mask; in x86_cpu_set_bit_prop()
8977 fp = op->opaque; in x86_cpu_register_bit_prop()
8978 assert(fp->w == w); in x86_cpu_register_bit_prop()
8979 fp->mask |= mask; in x86_cpu_register_bit_prop()
8982 fp->w = w; in x86_cpu_register_bit_prop()
8983 fp->mask = mask; in x86_cpu_register_bit_prop()
8996 const char *name = fi->feat_names[bitnr]; in x86_cpu_register_feature_bit_props()
9002 /* Property names should use "-" instead of "_". in x86_cpu_register_feature_bit_props()
9030 esa->size = 0; in x86_cpu_post_initfn()
9038 if (current_machine && current_machine->cgs) { in x86_cpu_post_initfn()
9040 X86_CONFIDENTIAL_GUEST(current_machine->cgs), (CPU(obj))); in x86_cpu_post_initfn()
9047 CPUX86State *env = &cpu->env; in x86_cpu_init_default_topo()
9049 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; in x86_cpu_init_default_topo()
9052 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); in x86_cpu_init_default_topo()
9053 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); in x86_cpu_init_default_topo()
9054 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); in x86_cpu_init_default_topo()
9061 CPUX86State *env = &cpu->env; in x86_cpu_initfn()
9065 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", in x86_cpu_initfn()
9067 NULL, NULL, (void *)env->features); in x86_cpu_initfn()
9068 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", in x86_cpu_initfn()
9070 NULL, NULL, (void *)cpu->filtered_features); in x86_cpu_initfn()
9074 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); in x86_cpu_initfn()
9075 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); in x86_cpu_initfn()
9077 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); in x86_cpu_initfn()
9080 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); in x86_cpu_initfn()
9081 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); in x86_cpu_initfn()
9082 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); in x86_cpu_initfn()
9083 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); in x86_cpu_initfn()
9084 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); in x86_cpu_initfn()
9085 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); in x86_cpu_initfn()
9086 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); in x86_cpu_initfn()
9087 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); in x86_cpu_initfn()
9088 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); in x86_cpu_initfn()
9089 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); in x86_cpu_initfn()
9090 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); in x86_cpu_initfn()
9091 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); in x86_cpu_initfn()
9092 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); in x86_cpu_initfn()
9093 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); in x86_cpu_initfn()
9094 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); in x86_cpu_initfn()
9095 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); in x86_cpu_initfn()
9096 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); in x86_cpu_initfn()
9097 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); in x86_cpu_initfn()
9098 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); in x86_cpu_initfn()
9099 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); in x86_cpu_initfn()
9100 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); in x86_cpu_initfn()
9104 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); in x86_cpu_initfn()
9105 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; in x86_cpu_initfn()
9106 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); in x86_cpu_initfn()
9108 if (xcc->model) { in x86_cpu_initfn()
9109 x86_cpu_load_model(cpu, xcc->model); in x86_cpu_initfn()
9117 return cpu->apic_id; in x86_cpu_get_arch_id()
9125 return cpu->env.cr[0] & CR0_PG_MASK; in x86_cpu_get_paging_enabled()
9133 cpu->env.eip = value; in x86_cpu_set_pc()
9141 return cpu->env.eip + cpu->env.segs[R_CS].base; in x86_cpu_get_pc()
9148 CPUX86State *env = &cpu->env; in x86_cpu_pending_interrupt()
9157 if (env->hflags2 & HF2_GIF_MASK) { in x86_cpu_pending_interrupt()
9159 !(env->hflags & HF_SMM_MASK)) { in x86_cpu_pending_interrupt()
9162 !(env->hflags2 & HF2_NMI_MASK)) { in x86_cpu_pending_interrupt()
9167 (((env->hflags2 & HF2_VINTR_MASK) && in x86_cpu_pending_interrupt()
9168 (env->hflags2 & HF2_HIF_MASK)) || in x86_cpu_pending_interrupt()
9169 (!(env->hflags2 & HF2_VINTR_MASK) && in x86_cpu_pending_interrupt()
9170 (env->eflags & IF_MASK && in x86_cpu_pending_interrupt()
9171 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { in x86_cpu_pending_interrupt()
9173 } else if (env->hflags2 & HF2_VGIF_MASK) { in x86_cpu_pending_interrupt()
9175 (env->eflags & IF_MASK) && in x86_cpu_pending_interrupt()
9176 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { in x86_cpu_pending_interrupt()
9187 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; in x86_cpu_has_work()
9194 CPUX86State *env = &cpu->env; in x86_disas_set_info()
9196 info->endian = BFD_ENDIAN_LITTLE; in x86_disas_set_info()
9197 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 in x86_disas_set_info()
9198 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 in x86_disas_set_info()
9201 info->cap_arch = CS_ARCH_X86; in x86_disas_set_info()
9202 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 in x86_disas_set_info()
9203 : env->hflags & HF_CS32_MASK ? CS_MODE_32 in x86_disas_set_info()
9205 info->cap_insn_unit = 1; in x86_disas_set_info()
9206 info->cap_insn_split = 8; in x86_disas_set_info()
9218 hflags = env->hflags & HFLAG_COPY_MASK; in x86_update_hflags()
9219 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; in x86_update_hflags()
9220 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); in x86_update_hflags()
9221 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & in x86_update_hflags()
9223 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); in x86_update_hflags()
9225 if (env->cr[4] & CR4_OSFXSR_MASK) { in x86_update_hflags()
9229 if (env->efer & MSR_EFER_LMA) { in x86_update_hflags()
9233 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { in x86_update_hflags()
9236 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> in x86_update_hflags()
9237 (DESC_B_SHIFT - HF_CS32_SHIFT); in x86_update_hflags()
9238 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> in x86_update_hflags()
9239 (DESC_B_SHIFT - HF_SS32_SHIFT); in x86_update_hflags()
9240 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || in x86_update_hflags()
9244 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | in x86_update_hflags()
9245 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; in x86_update_hflags()
9248 env->hflags = hflags; in x86_update_hflags()
9253 /* apic_id = 0 by default for *-user, see commit 9886e834 */
9254 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
9255 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
9256 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
9257 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0),
9258 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
9259 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
9261 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
9262 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
9263 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
9264 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1),
9265 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
9266 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
9268 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9270 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT),
9272 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
9274 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
9276 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
9278 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
9280 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
9282 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
9284 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
9286 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
9288 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
9290 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
9292 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
9294 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
9296 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
9298 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
9300 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
9302 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
9304 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features,
9306 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features,
9308 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features,
9310 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features,
9312 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features,
9314 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
9317 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features,
9320 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
9321 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false),
9324 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build,
9326 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major,
9328 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor,
9330 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0),
9331 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0),
9332 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0),
9336 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
9338 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
9339 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1),
9340 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
9341 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
9342 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
9343 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
9348 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
9349 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
9350 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
9351 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0),
9352 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
9353 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
9354 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
9355 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
9356 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true),
9357 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true),
9359 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
9360 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid,
9362 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
9363 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
9364 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
9370 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
9371 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false),
9372 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false),
9377 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
9380 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
9386 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9387 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
9389 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
9391 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true),
9395 #include "hw/core/sysemu-cpu-ops.h"
9421 &xcc->parent_realize); in x86_cpu_common_class_init()
9423 &xcc->parent_unrealize); in x86_cpu_common_class_init()
9427 &xcc->parent_phases); in x86_cpu_common_class_init()
9428 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; in x86_cpu_common_class_init()
9430 cc->class_by_name = x86_cpu_class_by_name; in x86_cpu_common_class_init()
9431 cc->list_cpus = x86_cpu_list; in x86_cpu_common_class_init()
9432 cc->parse_features = x86_cpu_parse_featurestr; in x86_cpu_common_class_init()
9433 cc->dump_state = x86_cpu_dump_state; in x86_cpu_common_class_init()
9434 cc->set_pc = x86_cpu_set_pc; in x86_cpu_common_class_init()
9435 cc->get_pc = x86_cpu_get_pc; in x86_cpu_common_class_init()
9436 cc->gdb_read_register = x86_cpu_gdb_read_register; in x86_cpu_common_class_init()
9437 cc->gdb_write_register = x86_cpu_gdb_write_register; in x86_cpu_common_class_init()
9438 cc->get_arch_id = x86_cpu_get_arch_id; in x86_cpu_common_class_init()
9441 cc->sysemu_ops = &i386_sysemu_ops; in x86_cpu_common_class_init()
9444 cc->tcg_ops = &x86_tcg_ops; in x86_cpu_common_class_init()
9447 cc->gdb_arch_name = x86_gdb_arch_name; in x86_cpu_common_class_init()
9449 cc->gdb_core_xml_file = "i386-64bit.xml"; in x86_cpu_common_class_init()
9451 cc->gdb_core_xml_file = "i386-32bit.xml"; in x86_cpu_common_class_init()
9453 cc->disas_set_info = x86_disas_set_info; in x86_cpu_common_class_init()
9455 dc->user_creatable = true; in x86_cpu_common_class_init()
9469 object_class_property_add_str(oc, "model-id", in x86_cpu_common_class_init()
9472 object_class_property_add(oc, "tsc-frequency", "int", in x86_cpu_common_class_init()
9476 * The "unavailable-features" property has the same semantics as in x86_cpu_common_class_init()
9477 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" in x86_cpu_common_class_init()
9481 object_class_property_add(oc, "unavailable-features", "strList", in x86_cpu_common_class_init()
9486 object_class_property_add(oc, "crash-information", "GuestPanicInformation", in x86_cpu_common_class_init()
9511 /* "base" CPU model, used by query-cpu-model-expansion */
9516 xcc->static_model = true; in x86_cpu_base_class_init()
9517 xcc->migration_safe = true; in x86_cpu_base_class_init()
9518 xcc->model_description = "base CPU model type with no features enabled"; in x86_cpu_base_class_init()
9519 xcc->ordering = 8; in x86_cpu_base_class_init()