Lines Matching full:i
78 for (int i = 0; i < ctx->future_vregs_idx; i++) { in ctx_future_vreg_off() local
79 if (ctx->future_vregs_num[i] == regnum) { in ctx_future_vreg_off()
80 return offsetof(CPUHexagonState, future_VRegs[i]); in ctx_future_vreg_off()
86 for (int i = 0; i < num; i++) { in ctx_future_vreg_off() local
87 ctx->future_vregs_num[ctx->future_vregs_idx + i] = regnum++; in ctx_future_vreg_off()
100 for (int i = 0; i < ctx->tmp_vregs_idx; i++) { in ctx_tmp_vreg_off() local
101 if (ctx->tmp_vregs_num[i] == regnum) { in ctx_tmp_vreg_off()
102 return offsetof(CPUHexagonState, tmp_VRegs[i]); in ctx_tmp_vreg_off()
108 for (int i = 0; i < num; i++) { in ctx_tmp_vreg_off() local
109 ctx->tmp_vregs_num[ctx->tmp_vregs_idx + i] = regnum++; in ctx_tmp_vreg_off()
227 for (int i = 0; i < pkt->num_insns; i++) { in check_for_attrib() local
228 if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) { in check_for_attrib()
238 for (int i = 0; i < pkt->num_insns; i++) { in need_slot_cancelled() local
239 uint16_t opcode = pkt->insn[i].opcode; in need_slot_cancelled()
253 for (int i = 0; i < pkt->num_insns; i++) { in need_next_PC() local
254 uint16_t opcode = pkt->insn[i].opcode; in need_next_PC()
347 for (int i = 0; i < ctx->reg_log_idx; i++) { in need_commit() local
348 int rnum = ctx->reg_log[i]; in need_commit()
386 for (int i = 0; i < pkt->num_insns; i++) { in analyze_packet() local
387 Insn *insn = &pkt->insn[i]; in analyze_packet()
404 int i; in gen_start_packet() local
424 for (i = 0; i < STORES_MAX; i++) { in gen_start_packet()
425 ctx->store_width[i] = 0; in gen_start_packet()
429 for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { in gen_start_packet()
430 ctx->new_value[i] = NULL; in gen_start_packet()
432 for (i = 0; i < NUM_PREGS; i++) { in gen_start_packet()
433 ctx->new_pred_value[i] = NULL; in gen_start_packet()
459 /* Preload the predicated registers into get_result_gpr(ctx, i) */ in gen_start_packet()
462 i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); in gen_start_packet()
463 while (i < TOTAL_PER_THREAD_REGS) { in gen_start_packet()
464 tcg_gen_mov_tl(get_result_gpr(ctx, i), hex_gpr[i]); in gen_start_packet()
465 i = find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS, in gen_start_packet()
466 i + 1); in gen_start_packet()
475 for (i = 0; i < ctx->preg_log_idx; i++) { in gen_start_packet()
476 int pred_num = ctx->preg_log[i]; in gen_start_packet()
484 i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS); in gen_start_packet()
485 while (i < NUM_VREGS) { in gen_start_packet()
487 ctx_future_vreg_off(ctx, i, 1, true); in gen_start_packet()
488 intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]); in gen_start_packet()
493 i = find_next_bit(ctx->predicated_future_vregs, NUM_VREGS, i + 1); in gen_start_packet()
497 i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS); in gen_start_packet()
498 while (i < NUM_VREGS) { in gen_start_packet()
500 ctx_tmp_vreg_off(ctx, i, 1, true); in gen_start_packet()
501 intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]); in gen_start_packet()
506 i = find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + 1); in gen_start_packet()
518 for (int i = 0; i < pkt->num_insns; i++) { in is_gather_store_insn() local
519 Insn *in = &pkt->insn[i]; in is_gather_store_insn()
570 int i; in gen_reg_writes() local
577 for (i = 0; i < ctx->reg_log_idx; i++) { in gen_reg_writes()
578 int reg_num = ctx->reg_log[i]; in gen_reg_writes()
599 for (int i = 0; i < ctx->preg_log_idx; i++) { in gen_pred_writes() local
600 int pred_num = ctx->preg_log[i]; in gen_pred_writes()
607 for (int i = 0; i < pkt->num_insns; i++) { in slot_is_predicated() local
608 if (pkt->insn[i].slot == slot_num) { in slot_is_predicated()
609 return GET_ATTRIB(pkt->insn[i].opcode, A_CONDEXEC); in slot_is_predicated()
727 int i; in pkt_has_hvx_store() local
728 for (i = 0; i < pkt->num_insns; i++) { in pkt_has_hvx_store()
729 int opcode = pkt->insn[i].opcode; in pkt_has_hvx_store()
739 int i; in gen_commit_hvx() local
748 * for (i = 0; i < ctx->vreg_log_idx; i++) { in gen_commit_hvx()
749 * int rnum = ctx->vreg_log[i]; in gen_commit_hvx()
753 for (i = 0; i < ctx->vreg_log_idx; i++) { in gen_commit_hvx()
754 int rnum = ctx->vreg_log[i]; in gen_commit_hvx()
763 * for (i = 0; i < ctx->qreg_log_idx; i++) { in gen_commit_hvx()
764 * int rnum = ctx->qreg_log[i]; in gen_commit_hvx()
768 for (i = 0; i < ctx->qreg_log_idx; i++) { in gen_commit_hvx()
769 int rnum = ctx->qreg_log[i]; in gen_commit_hvx()
789 for (int i = 0; i < num_insns; i++) { in update_exec_counters() local
790 if (!pkt->insn[i].is_endloop && in update_exec_counters()
791 !pkt->insn[i].part1 && in update_exec_counters()
792 !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) { in update_exec_counters()
795 if (GET_ATTRIB(pkt->insn[i].opcode, A_CVI)) { in update_exec_counters()
911 int i; in decode_and_translate_packet() local
923 for (i = 0; i < pkt.num_insns; i++) { in decode_and_translate_packet()
924 ctx->insn = &pkt.insn[i]; in decode_and_translate_packet()
1049 int i; in hexagon_translate_init() local
1053 for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { in hexagon_translate_init()
1054 hex_gpr[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1055 offsetof(CPUHexagonState, gpr[i]), in hexagon_translate_init()
1056 hexagon_regnames[i]); in hexagon_translate_init()
1061 for (i = 0; i < NUM_PREGS; i++) { in hexagon_translate_init()
1062 hex_pred[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1063 offsetof(CPUHexagonState, pred[i]), in hexagon_translate_init()
1064 hexagon_prednames[i]); in hexagon_translate_init()
1074 for (i = 0; i < STORES_MAX; i++) { in hexagon_translate_init()
1075 snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); in hexagon_translate_init()
1076 hex_store_addr[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1077 offsetof(CPUHexagonState, mem_log_stores[i].va), in hexagon_translate_init()
1078 store_addr_names[i]); in hexagon_translate_init()
1080 snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); in hexagon_translate_init()
1081 hex_store_width[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1082 offsetof(CPUHexagonState, mem_log_stores[i].width), in hexagon_translate_init()
1083 store_width_names[i]); in hexagon_translate_init()
1085 snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i); in hexagon_translate_init()
1086 hex_store_val32[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1087 offsetof(CPUHexagonState, mem_log_stores[i].data32), in hexagon_translate_init()
1088 store_val32_names[i]); in hexagon_translate_init()
1090 snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i); in hexagon_translate_init()
1091 hex_store_val64[i] = tcg_global_mem_new_i64(tcg_env, in hexagon_translate_init()
1092 offsetof(CPUHexagonState, mem_log_stores[i].data64), in hexagon_translate_init()
1093 store_val64_names[i]); in hexagon_translate_init()
1095 for (i = 0; i < VSTORES_MAX; i++) { in hexagon_translate_init()
1096 snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i); in hexagon_translate_init()
1097 hex_vstore_addr[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1098 offsetof(CPUHexagonState, vstore[i].va), in hexagon_translate_init()
1099 vstore_addr_names[i]); in hexagon_translate_init()
1101 snprintf(vstore_size_names[i], NAME_LEN, "vstore_size_%d", i); in hexagon_translate_init()
1102 hex_vstore_size[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1103 offsetof(CPUHexagonState, vstore[i].size), in hexagon_translate_init()
1104 vstore_size_names[i]); in hexagon_translate_init()
1106 snprintf(vstore_pending_names[i], NAME_LEN, "vstore_pending_%d", i); in hexagon_translate_init()
1107 hex_vstore_pending[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1108 offsetof(CPUHexagonState, vstore_pending[i]), in hexagon_translate_init()
1109 vstore_pending_names[i]); in hexagon_translate_init()