target/hexagon/macros.h

2  *  Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
41     fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
47             fINSERT_BITS(env->new_value_usr, \
51             fINSERT_BITS(env->gpr[HEX_REG_USR], \
60  * Section 5.5 of the Hexagon V67 Programmer's Reference Manual
86         if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
87             probe_noshuf_load(VA, SIZE, ctx->mem_idx); \
97         if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
98             probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
101         if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
109         tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_SB); \
114         tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_UB); \
119         tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_LE | MO_SW); \
124         tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_LE | MO_UW); \
129         tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_LE | MO_SL); \
134         tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_LE | MO_UL); \
139         tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_LE | MO_UQ); \
193 #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); }
199 #define fABS(A) (((A) < 0) ? (-(A)) : (A))
207     (((HIBIT) - (LOWBIT) + 1) ? \
208         extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \
212         int width = ((HIBIT) - (LOWBIT) + 1); \
256         (((int64_t)(VAL)) < 0) ? 0 : ((1LL << (N)) - 1); \
261         ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \
266         ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
270         ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
321      * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual  in gen_read_ireg()
342 #define fREAD_LR() (env->gpr[HEX_REG_LR])
345 #define fREAD_LC0 (env->gpr[HEX_REG_LC0])
346 #define fREAD_LC1 (env->gpr[HEX_REG_LC1])
347 #define fREAD_SA0 (env->gpr[HEX_REG_SA0])
348 #define fREAD_SA1 (env->gpr[HEX_REG_SA1])
349 #define fREAD_FP() (env->gpr[HEX_REG_FP])
351 /* Figure out how to get insn->extension_valid to helper */
353     (insn->extension_valid ? 0 : env->gpr[HEX_REG_GP])
355 #define fREAD_GP() (env->gpr[HEX_REG_GP])
411         int32_t maxv = (1 << U) - 1; \
412         int32_t minv = -(1 << U); \
416 #define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1))))))
484     (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
491     (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
494     (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \
502                         << ((-(SHAMT)) - 1)) << 1, (SRC)) \
510                                  ((sizeof(SRC) * 8) - (SHAMT))))))
514                                  ((sizeof(SRC) * 8) - (SHAMT))))))
535 #define fGET_FRAMEKEY() (env->gpr[HEX_REG_FRAMEKEY])
540 #define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */
548     gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx);
552 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot)
627 #define fCL1_2(VAL) (clz32(~(uint16_t)(VAL) & 0xffff) - 16)
640     (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset)
642     fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
649         ctx->dczero_addr = tcg_temp_new(); \
650         tcg_gen_mov_tl(ctx->dczero_addr, (REG)); \