hexagon/imported/shift.idef

2  *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
19  * S-type Instructions
32     "Arithmetic Shift Right by Register", \
39     "Arithmetic Shift Left by Register", \
46     "Logical Shift Right by Register", \
53     "Logical Shift Left by Register", \
63 RSHIFTTYPES(r_nac,Rx,Rs,4_8,-,RxV,fECHO,,)
64 RSHIFTTYPES(p_nac,Rxx,Rss,8_8,-,RxxV,fECHO,,)
75 /* Register shift with saturation */
78     "Arithmetic Shift Right by Register", \
85     "Arithmetic Shift Left by Register", \
99     "Arithmetic Shift Right by Immediate", \
103     "Logical Shift Right by Immediate", \
107     "Shift Left by Immediate", \
110     "Rotate Left by Immediate", \
127     "Logical Shift Right by Register", \
130     "Shift Left by Register", \
133     "Rotate Left by Immediate", \
142 ISHIFTTYPES(r_nac,5,Rx,Rs,4_4,-,RxV,fECHO,,)
143 ISHIFTTYPES(p_nac,6,Rxx,Rss,8_8,-,RxxV,fECHO,,)
157        "Shift right with round",
161 Q6INSN(S2_asr_i_p_rnd,"Rdd32=asr(Rss32,#u6):rnd",ATTRIBS(), "Shift right with round",
169 Q6INSN(S4_lsli,"Rd32=lsl(#s6,Rt32)",ATTRIBS(), "Shift an immediate left by register amount",
179     "Shift left by small amount and add",
185 Q6INSN(S4_andi_##TAGEND,"Rx32=and(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)&INNERSEM;})\
186 Q6INSN(S4_ori_##TAGEND, "Rx32=or(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)|INNERSEM;})\
187 Q6INSN(S4_addi_##TAGEND,"Rx32=add(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)+INNERSEM;})\
188 Q6INSN(S4_subi_##TAGEND,"Rx32=sub(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)-INNERSEM;})
201   RddV = (fLSHIFTR(RssV,uiV*8,8_8))|(fASHIFTL(RttV,((8-uiV)*8),8_8));
206 { RddV = fLSHIFTR(RssV,(PuV&0x7)*8,8_8)|(fASHIFTL(RttV,(8-(PuV&0x7))*8,8_8));})
256     RxV &= ~(((fCONSTLL(1)<<width)-1)<<offset);
258     RxV |= ((RsV & ((fCONSTLL(1)<<width)-1)) << offset);
340     RxxV &= ~(((fCONSTLL(1)<<width)-1)<<offset);
342     RxxV |= ((RssV & ((fCONSTLL(1)<<width)-1)) << offset);
369     RdV = ((1<<uiV)-1) << UiV;
381     fHIDE(size8u_t) mask = ((fCONSTLL(1)<<width)-1);
416     fHIDE(size8u_t) mask = ((fCONSTLL(1)<<width)-1);
520     "Vector Arithmetic Shift Right by Immediate",
530     "Vector Logical Shift Right by Immediate",
539     "Vector Arithmetic Shift Left by Immediate",
550     "Vector Arithmetic Shift Right by Register",
559     "Vector Arithmetic Shift Right by Immediate with Round, Saturate, and Pack",
568     "Vector Arithmetic Shift Right by Immediate with Saturate and Pack",
579     "Vector Arithmetic Shift Right by Immediate with Round",
589     "Vector Arithmetic Shift Left by Register",
600     "Vector Logical Shift Right by Register",
610     "Vector Logical Shift Left by Register",
624     "Vector Arithmetic Shift Right by Immediate",
635     "Vector Arithmetic Shift Right by Immediate with Truncate and Pack",
644     "Vector Arithmetic Shift Right truncate and Pack",
654     "Vector Logical Shift Right by Immediate",
663     "Vector Arithmetic Shift Left by Immediate",
674     "Vector Arithmetic Shift Right by Register",
685     "Vector Arithmetic Shift Left by Register",
695     "Vector Logical Shift Right by Register",
706     "Vector Logical Shift Left by Register",
1017 "Count leading sign bits - 1", { if (RsV == 0) { RdV = 0; } else { RdV = (fMAX(fCL1_4(RsV),fCL1_4(~…
1024 "Count leading sign bits - 1", { if (RssV == 0) { RdV = 0; }
1025 else { RdV = (fMAX(fCL1_8(RssV),fCL1_8(~RssV)))-1;}})
1053     rLPS  = rLPS << 23;   /* left aligned */
1056     rMPS= (range&0xff800000) - rLPS;
1071         fINSERT_RANGE(RddV,8,8,((!state)?(1-valMPS):(valMPS)));
1073         fSETWORD(1,RddV,(offset-rMPS));