hexagon/idef-parser/README.rst

4 idef-parser is a small compiler able to translate the Hexagon ISA description
10 To better understand the scope of the idef-parser, we'll explore an applicative
11 example. Let's start by one of the simplest Hexagon instruction: the ``add``.
13 The ISA description language represents the ``add`` instruction as
22 idef-parser will compile the above code into the following code:
36 The output of the compilation process will be a function, containing the
37 tinycode generator code, implementing the correct semantics. That function will
38 not access any global variable, because all the accessed data structures will be
39 passed explicitly as function parameters. Among the passed parameters we will
40 have TCGv (tinycode variables) representing the input and output registers of
41 the architecture, integers representing the immediates that come from the code,
42 and other data structures which hold information about the disassemblation
45 Let's begin by describing the input code. The ``add`` instruction is associated
47 variants of the same instruction, and expresses the class to which the
48 instruction belongs, in this case ``A2`` corresponds to the Hexagon
51 After the instruction identifier, we have a series of parameters that represents
52 TCG variables that will be passed to the generated function. Parameters marked
53 with ``in`` are already initialized, while the others are output parameters.
57 -  Fill in the output function signature with the correct TCGv registers
58 -  Fill in the output function signature with the immediate integers
59 -  Keep track of which registers, among the declared one, have been
62 Let's now observe the actual instruction description code, in this case:
68 This code is composed by a subset of the C syntax, and is the result of the
69 application of some macro definitions contained in the ``macros.h`` file.
71 This file is used to reduce the complexity of the input language where complex
72 variants of similar constructs can be mapped to a unique primitive, so that the
75 As you may notice, the description code modifies the registers which have been
76 declared by the declaration statements. In this case all the three registers
80 Now let's have a quick look at the generated code, line by line.
86 This code starts by declaring a temporary TCGv to hold the result from the sum
93 Then, we are generating the sum tinycode operator between the selected
94 registers, storing the result in the just declared temporary.
100 The result of the addition is now stored in the temporary, we move it into the
102 perform some optimizations on the tinycode, reducing the unnecessary copy.
107 Before moving on to the structure of idef-parser itself, let us spend some words
108 on its' input. There are two preprocessing steps applied to the generated
117 pseudo code, output into ``idef_parser_input.h.inc``. For instance, the
130 we obtain the pseudo code
140 The second step is to expand macros into a form suitable for our parser.
141 These macros are defined in ``idef-parser/macros.h.inc`` and the step is
142 carried out by the ``prepare`` script which runs the C preprocessor on
146 To finish the above example, after preprocessing ``J2_jumpr`` we obtain
155 signifying a write to the Program Counter ``PC``.  Note, that ``PC`` in
156 this expression is not a variable in the strict C sense since it is not
163 The idef-parser is built using the ``flex`` and ``bison``.
165 ``flex`` is used to split the input string into tokens, each described using a
166 regular expression. The token description is contained in the
167 ``idef-parser.lex`` source file. The flex-generated scanner takes care also to
168 extract from the input text other meaningful information, e.g., the numerical
169 value in case of an immediate constant, and decorates the token with the
172 ``bison`` is used to generate the actual parser, starting from the parsing
173 description contained in the ``idef-parser.y`` file. The generated parser
174 executes the ``main`` function at the end of the ``idef-parser.y`` file, which
175 opens input and output files, creates the parsing context, and eventually calls
176 the ``yyparse()`` function, which starts the execution of the LALR(1) parser
178 information about LALR parsing techniques). The LALR(1) parser, whenever it has
179 to shift a token, calls the ``yylex()`` function, which is defined by the
180 flex-generated code, and reads the input file returning the next scanned token.
182 The tokens are mapped on the source language grammar, defined in the
183 ``idef-parser.y`` file to build a unique syntactic tree, according to the
186 The grammar describes the whole file which contains the Hexagon instruction
187 descriptions, therefore it starts from the ``input`` nonterminal, which is a
188 list of instructions, each instruction is represented by the following grammar
189 rule, representing the structure of the input file shown above:
224 With this initial portion of the grammar we are defining the instruction, its'
225 arguments, and its' statements. Each argument is defined by the
239 Note, the only local variable allowed to be used as an argument is the effective
248 Allowed in the input code are C language expressions with a few exceptions
252 ``TCGv_i32`` or ``TCGv_i64`` depending on the register size. Similarly, ``UiV``,
255 Also, as mentioned earlier, the names ``PC``, ``SP``, ``FP``, etc. are used to
256 refer to Hexagon registers such as the program counter, stack pointer, and frame
258 ``PC = ...``, and reads correspond to uses of the variable ``PC``.
260 Moreover, another example of one such exception is the selective expansion of
261 macros present in ``macros.h``. As an example, consider the ``fABS`` macro which
268 and returns the absolute value of the argument ``A``. This macro is not included
271 ``tcg_gen_abs_<width>``, compared to the full ternary expression above. Loads of
272 macros in ``macros.h`` are kept unexpanded to aid in parsing, as seen in the
278 folding the expression.
283 Similarly to C, variables in the input code must be explicitly declared, such as
286 generators the previous declarations are mapped to
295 which are later automatically freed at the end of the function they're declared
297 specified in the following table (without permutation of keywords)
329 which will feature the variable name as a decoration. For a variable declaration
330 idef-parser calls ``gen_varid_allocate`` with the ``VARID`` token to save the
331 name, size, and bit width of the newly declared variable. In addition, this
333 and error message if that is the case. Upon use of a variable, the ``VARID``
334 token is used to lookup the size and bit width of the variable.
340 the signedness and bit width of the operations.
342 The type of each ``rvalue`` is determined by two attributes: its bit width
345 For each operation, the type of ``rvalue``\ s influence the way in which the
348 will be a logical shift. If one of the two operands is signed, and the other
349 is unsigned, the operation will be signed.
351 The bit width also influences the outcome of the operations, in particular while
352 the input languages features a fine granularity type system, with types of 8,
353 16, 32, 64 (and more for vectorial instructions) bits, the tinycode only
354 features 32 and 64 bit widths. We propagate as much as possible the fine
355 granularity type, until the value has to be used inside an operation between
356 ``rvalue``\ s; in that case if one of the two operands is greater than 32 bits
357 we promote the whole operation to 64 bit, taking care of properly extending the
358 two operands. Fortunately, the most critical instructions already feature
362 The combination of ``rvalue``\ s are handled through the use of the
364 the appropriate compile-time or run-time emission of operations to perform the
370 ``control_statement``\ s are all the statements which modify the order of
371 execution of the generated code according to input parameters. They are expanded
372 by the following grammar rule:
382 ``if_statement``\ s require the emission of labels and branch instructions which
383 effectively perform conditional jumps (``tcg_gen_brcondi``) according to the
384 value of an expression. Note, the tinycode generators we produce for conditional
386 do not reproduce short-circuiting of the ``&&`` operator, and use of the ``||``
387 operator is disallowed. All the predicated instructions, and in general all the
395 are handled using the conditional move tinycode instruction
396 (``tcg_gen_movcond``), which avoids the additional complexity of managing labels
399 Instead, regarding the ``for`` loops, exploiting the fact that they always
402 possible because the loops will be executed in the QEMU code, leading to the
403 consequential unrolling of the for loop, since the tinycode generator
404 instructions will be executed multiple times, and the respective generated
405 tinycode will represent the unrolled execution of the loop.
410 All the helper functions in ``idef-parser.y`` carry two fixed parameters, which
411 are the parsing context ``c`` and the ``YYLLOC`` location information. The
412 context is explicitly passed to all the functions because the parser we generate
414 therefore the instruction compilation could easily be parallelized in the
415 future. Finally for each rule we propagate information about the location of the
416 involved tokens to generate pretty error reporting, able to highlight the
417 portion of the input code which generated each error.
422 Developing the idef-parser can lead to two types of errors: compile-time errors
426 the described grammar. Conflicts forbid the grammar to produce a unique
427 derivation tree, thus must be solved (except for the dangling else problem,
428 which is marked as expected through the ``%expect 1`` Bison option).
435 some counterexamples which highlight ambiguous derivations, passing the
437 redesigning the grammar in an unambiguous way or by setting the token priority
438 correctly, while reduce/reduce conflicts are solved by redesigning the
439 interested part of the grammar.
442 are hard to detect, since the ``var`` token will catch everything which is not
443 caught by other tokens, but easy to fix, because most of the time a simple
447 parsing error reports the fragment of the input text which was involved in the
451 suggestions to make each instruction proceed to the next step.
455    Means that the parsing of the input code relative to that instruction failed,
456    this could be due to a lexical error or to some mismatch between the order of
458    identified and mapped, and that there is a rule matching the token sequence
463    This instruction class contains all the instructions which are emitted but
464    fail to compile when included in QEMU. The compilation errors are shown by
465    the QEMU building process and will lead to fixing the bug.  Most common
466    errors regard the mismatch of parameters for tinycode generator functions,
467    which boil down to errors in the idef-parser type system.
472    the QEMU or the harness tests, these cases must be handled manually by
473    looking into the failing tests and looking at the generated tinycode
474    generator instruction and at the generated tinycode itself. Tip: handle the
477    multi-threaded test fail, fixing all the other tests will be the easier
478    option, hoping that the multi-threaded one will be indirectly fixed.
480    An example of debugging this type of failure is provided in the following
485    This is the final goal for each instruction, meaning that the instruction
486    passes the test suite.
489 to compare the execution trace of your implementation with the reference
491 where the instruction pass the test, and run it with the following command:
498 And do the same for your implementation, the generated execution traces will be
499 inherently aligned and can be inspected for behavioral differences using the
505 The goal of this section is to provide a complete example of debugging
508 Let's first introduce a bug in the tinycode generator of the ``A2_add``
522 Here the bug, albeit hard to spot, is in ``tcg_gen_add_i32(tmp_0, RsV, RsV);``
524 This particular bug is a bit tricky to pinpoint when debugging, since the
526 fail and therefore not provide a lot of information about the bug.
528 For example, let's run the ``check-tcg`` tests
537 In the output, we find a failure in the very first test case ``float_convs``
539 well. At this point we have no clue where the actual bug lies, and need to start
540 ruling out instructions. As such a good starting point is to utilize the debug
541 options ``-d in_asm,cpu`` of QEMU to inspect the Hexagon instructions being run,
542 alongside the CPU state. We additionally need a working version of the emulator
549 will disable the idef-parser for all instructions and fallback on manual
552 our binary with the incorrect tinycode generators, we can compare the CPU state
553 between the two versions
560 Looking at ``diff -u out_buggy out_working`` shows us that the CPU state begins
561 to diverge on line 141, with an incorrect value in the ``R1`` register
575 If we also look into ``out_buggy`` directly we can inspect the input assembly
576 which the caused the incorrect CPU state, around line 141 we find
592 Importantly, we see some Hexagon assembly followed by a dump of the CPU state,
593 now the CPU state is actually dumped before the input assembly above is ran.
594 As such, we are actually interested in the instructions ran before this.
619 Remember, the instructions on lines 56-65 are ran on the CPU state shown below
620 instructions, and as the CPU state has not diverged at this point, we know the
621 starting state is accurate. The bug must then lie within the instructions shown
632 point it might be easy enough to go directly to the emitted code for the
634 ``./qemu-heaxgon -d op,in_asm float_conv`` where we find for the following
635 tinycode for the Hexagon ``add`` instruction
651 The main limitation of the current parser is given by the syntax-driven nature
652 of the Bison-generated parsers. This has the severe implication of only being
653 able to generate code in the order of evaluation of the various rules, without,
654 in any case, being able to backtrack and alter the generated code.
656 An example limitation is highlighted by this statement of the input language:
663 proper control flow statements, which emit a jump to the first or to the second
665 the ternary assignment, the code evaluating the two assignments will be already
674 Which can be easily matched by the following parser rules:
688 Another example that highlight the limitation of the flex/bison parser can be
689 found even in the add operation we already saw:
697 The fact that we cannot directly use ``RdV`` as the destination of the sum is a
698 consequence of the syntax-driven nature of the parser. In fact when we parse the
699 assignment, the ``rvalue`` token, representing the sum has already been reduced,
700 and thus its code emitted and unchangeable. We rely on the fact that QEMU will
701 optimize our code reducing the useless move operations and the relative
704 A possible improvement of the parser regards the support for vectorial
705 instructions and floating point instructions, which will require the extension
706 of the scanner, the parser, and a partial re-design of the type system, allowing
707 to build the vectorial semantics over the available vectorial tinycode generator
710 A more radical improvement will use the parser, not to generate directly the
711 tinycode generator code, but to generate an intermediate representation like the
712 LLVM IR, which in turn could be compiled using the clang TCG backend. That code
713 could be furtherly optimized, overcoming the limitations of the syntax-driven