Lines Matching +full:pre +full:- +full:processing
4 * Copyright (c) 2019-2020 Michael Rolnik
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 #include "qemu/qemu-print.h"
25 #include "exec/translation-block.h"
26 #include "tcg/tcg-op.h"
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
34 #include "exec/helper-info.c.inc"
42 * https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests
99 * A - instruction that can skip the next one
100 * B - instruction that can be skipped. this depends on execution of A
109 * if (ctx->skip_cond != TCG_COND_NEVER) {
176 return translator_lduw(ctx->env, &ctx->base, ctx->npc++ * 2); in next_word()
186 if (!avr_feature(ctx->env, feature)) { in avr_have_feature()
188 ctx->base.is_jmp = DISAS_NORETURN; in avr_have_feature()
195 #include "decode-insn.c.inc"
207 * - gen_add_CHf()
208 * - gen_add_Vf()
209 * - gen_sub_CHf()
210 * - gen_sub_Vf()
211 * - gen_NSf()
212 * - gen_ZNSf()
299 TCGv Rd = cpu_r[a->rd]; in trans_ADD()
300 TCGv Rr = cpu_r[a->rr]; in trans_ADD()
322 TCGv Rd = cpu_r[a->rd]; in trans_ADC()
323 TCGv Rr = cpu_r[a->rr]; in trans_ADC()
341 * Adds an immediate value (0 - 63) to a register pair and places the result
353 TCGv RdL = cpu_r[a->rd]; in trans_ADIW()
354 TCGv RdH = cpu_r[a->rd + 1]; in trans_ADIW()
355 int Imm = (a->imm); in trans_ADIW()
384 TCGv Rd = cpu_r[a->rd]; in trans_SUB()
385 TCGv Rr = cpu_r[a->rr]; in trans_SUB()
388 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ in trans_SUB()
405 * and is very well suited for operations on the X, Y, and Z-pointers.
409 TCGv Rd = cpu_r[a->rd]; in trans_SUBI()
410 TCGv Rr = tcg_constant_i32(a->imm); in trans_SUBI()
413 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Imm */ in trans_SUBI()
432 TCGv Rd = cpu_r[a->rd]; in trans_SBC()
433 TCGv Rr = cpu_r[a->rr]; in trans_SBC()
437 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ in trans_SBC()
458 * SBCI -- Subtract Immediate with Carry
462 TCGv Rd = cpu_r[a->rd]; in trans_SBCI()
463 TCGv Rr = tcg_constant_i32(a->imm); in trans_SBCI()
467 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ in trans_SBCI()
488 * Subtracts an immediate value (0-63) from a register pair and places the
500 TCGv RdL = cpu_r[a->rd]; in trans_SBIW()
501 TCGv RdH = cpu_r[a->rd + 1]; in trans_SBIW()
502 int Imm = (a->imm); in trans_SBIW()
507 tcg_gen_subi_tl(R, Rd, Imm); /* R = Rd - Imm */ in trans_SBIW()
531 TCGv Rd = cpu_r[a->rd]; in trans_AND()
532 TCGv Rr = cpu_r[a->rr]; in trans_AND()
553 TCGv Rd = cpu_r[a->rd]; in trans_ANDI()
554 int Imm = (a->imm); in trans_ANDI()
571 TCGv Rd = cpu_r[a->rd]; in trans_OR()
572 TCGv Rr = cpu_r[a->rr]; in trans_OR()
592 TCGv Rd = cpu_r[a->rd]; in trans_ORI()
593 int Imm = (a->imm); in trans_ORI()
610 TCGv Rd = cpu_r[a->rd]; in trans_EOR()
611 TCGv Rr = cpu_r[a->rr]; in trans_EOR()
629 TCGv Rd = cpu_r[a->rd]; in trans_COM()
646 TCGv Rd = cpu_r[a->rd]; in trans_NEG()
650 tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */ in trans_NEG()
664 * Adds one -1- to the contents of register Rd and places the result in the
667 * multiple-precision computations. When operating on unsigned numbers, only
673 TCGv Rd = cpu_r[a->rd]; in trans_INC()
686 * Subtracts one -1- from the contents of register Rd and places the result
689 * multiple-precision computations. When operating on unsigned values, only
695 TCGv Rd = cpu_r[a->rd]; in trans_DEC()
697 tcg_gen_subi_tl(Rd, Rd, 1); /* Rd = Rd - 1 */ in trans_DEC()
708 * This instruction performs 8-bit x 8-bit -> 16-bit unsigned multiplication.
718 TCGv Rd = cpu_r[a->rd]; in trans_MUL()
719 TCGv Rr = cpu_r[a->rr]; in trans_MUL()
733 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication.
743 TCGv Rd = cpu_r[a->rd]; in trans_MULS()
744 TCGv Rr = cpu_r[a->rr]; in trans_MULS()
763 * This instruction performs 8-bit x 8-bit -> 16-bit multiplication of a
774 TCGv Rd = cpu_r[a->rd]; in trans_MULSU()
775 TCGv Rr = cpu_r[a->rr]; in trans_MULSU()
792 * This instruction performs 8-bit x 8-bit -> 16-bit unsigned
803 TCGv Rd = cpu_r[a->rd]; in trans_FMUL()
804 TCGv Rr = cpu_r[a->rr]; in trans_FMUL()
822 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication
833 TCGv Rd = cpu_r[a->rd]; in trans_FMULS()
834 TCGv Rr = cpu_r[a->rr]; in trans_FMULS()
857 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication
868 TCGv Rd = cpu_r[a->rd]; in trans_FMULSU()
869 TCGv Rr = cpu_r[a->rr]; in trans_FMULSU()
891 * DES iterations. The 64-bit data block (plaintext or ciphertext) is placed in
892 * the CPU register file, registers R0-R7, where LSB of data is placed in LSB
893 * of R0 and MSB of data is placed in MSB of R7. The full 64-bit key (including
894 * parity bits) is placed in registers R8- R15, organized in the register file
898 * plaintext. Intermediate results are stored in the register file (R0-R15)
903 * Processing Standards Publication 46). Intermediate results in this
928 ctx->base.is_jmp = DISAS_LOOKUP; in gen_jmp_ez()
934 ctx->base.is_jmp = DISAS_LOOKUP; in gen_jmp_z()
939 if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { in gen_push_ret()
944 } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { in gen_push_ret()
950 } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { in gen_push_ret()
963 if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { in gen_pop_ret()
966 } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { in gen_pop_ret()
970 } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { in gen_pop_ret()
986 const TranslationBlock *tb = ctx->base.tb; in gen_goto_tb()
988 if (translator_use_goto_tb(&ctx->base, dest)) { in gen_goto_tb()
996 ctx->base.is_jmp = DISAS_NORETURN; in gen_goto_tb()
1000 * Relative jump to an address within PC - 2K +1 and PC + 2K (words). For
1007 int dst = ctx->npc + a->imm; in trans_RJMP()
1016 * Register in the Register File. The Z-pointer Register is 16 bits wide and
1060 gen_goto_tb(ctx, 0, a->imm); in trans_JMP()
1066 * Relative call to an address within PC - 2K + 1 and PC + 2K (words). The
1070 * address location. The Stack Pointer uses a post-decrement scheme during
1075 int ret = ctx->npc; in trans_RCALL()
1076 int dst = ctx->npc + a->imm; in trans_RCALL()
1087 * Stack. See also RCALL. The Stack Pointer uses a post-decrement scheme during
1097 int ret = ctx->npc; in trans_ICALL()
1109 * memory space. See also ICALL. The Stack Pointer uses a post-decrement scheme
1119 int ret = ctx->npc; in trans_EICALL()
1129 * (See also RCALL). The Stack Pointer uses a post-decrement scheme during
1139 int Imm = a->imm; in trans_CALL()
1140 int ret = ctx->npc; in trans_CALL()
1156 ctx->base.is_jmp = DISAS_LOOKUP; in trans_RET()
1165 * the application program. The Stack Pointer uses a pre-increment scheme
1173 /* Need to return to main loop to re-evaluate interrupts. */ in trans_RETI()
1174 ctx->base.is_jmp = DISAS_EXIT; in trans_RETI()
1184 ctx->skip_cond = TCG_COND_EQ; in trans_CPSE()
1185 ctx->skip_var0 = cpu_r[a->rd]; in trans_CPSE()
1186 ctx->skip_var1 = cpu_r[a->rr]; in trans_CPSE()
1197 TCGv Rd = cpu_r[a->rd]; in trans_CP()
1198 TCGv Rr = cpu_r[a->rr]; in trans_CP()
1201 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ in trans_CP()
1218 TCGv Rd = cpu_r[a->rd]; in trans_CPC()
1219 TCGv Rr = cpu_r[a->rr]; in trans_CPC()
1223 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ in trans_CPC()
1246 TCGv Rd = cpu_r[a->rd]; in trans_CPI()
1247 int Imm = a->imm; in trans_CPI()
1251 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ in trans_CPI()
1267 TCGv Rr = cpu_r[a->rr]; in trans_SBRC()
1269 ctx->skip_cond = TCG_COND_EQ; in trans_SBRC()
1270 ctx->skip_var0 = tcg_temp_new(); in trans_SBRC()
1272 tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); in trans_SBRC()
1282 TCGv Rr = cpu_r[a->rr]; in trans_SBRS()
1284 ctx->skip_cond = TCG_COND_NE; in trans_SBRS()
1285 ctx->skip_var0 = tcg_temp_new(); in trans_SBRS()
1287 tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); in trans_SBRS()
1294 * lower 32 I/O Registers -- addresses 0-31.
1300 gen_inb(ctx, data, a->reg); in trans_SBIC()
1301 tcg_gen_andi_tl(data, data, 1 << a->bit); in trans_SBIC()
1302 ctx->skip_cond = TCG_COND_EQ; in trans_SBIC()
1303 ctx->skip_var0 = data; in trans_SBIC()
1311 * 32 I/O Registers -- addresses 0-31.
1317 gen_inb(ctx, data, a->reg); in trans_SBIS()
1318 tcg_gen_andi_tl(data, data, 1 << a->bit); in trans_SBIS()
1319 ctx->skip_cond = TCG_COND_NE; in trans_SBIS()
1320 ctx->skip_var0 = data; in trans_SBIS()
1328 * to PC in either direction (PC - 63 < = destination <= PC + 64). The
1338 switch (a->bit) { in trans_BRBC()
1368 gen_goto_tb(ctx, 0, ctx->npc + a->imm); in trans_BRBC()
1371 ctx->base.is_jmp = DISAS_CHAIN; in trans_BRBC()
1378 * PC in either direction (PC - 63 < = destination <= PC + 64). The parameter k
1387 switch (a->bit) { in trans_BRBS()
1417 gen_goto_tb(ctx, 0, ctx->npc + a->imm); in trans_BRBS()
1420 ctx->base.is_jmp = DISAS_CHAIN; in trans_BRBS()
1492 * changed. The Z-pointer Register is left unchanged by the operation. This
1497 if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { in gen_data_store()
1527 TCGv Rd = cpu_r[a->rd]; in trans_MOV()
1528 TCGv Rr = cpu_r[a->rr]; in trans_MOV()
1548 TCGv RdL = cpu_r[a->rd]; in trans_MOVW()
1549 TCGv RdH = cpu_r[a->rd + 1]; in trans_MOVW()
1550 TCGv RrL = cpu_r[a->rr]; in trans_MOVW()
1551 TCGv RrH = cpu_r[a->rr + 1]; in trans_MOVW()
1564 TCGv Rd = cpu_r[a->rd]; in trans_LDI()
1565 int imm = a->imm; in trans_LDI()
1577 * A 16-bit address must be supplied. Memory access is limited to the current
1586 TCGv Rd = cpu_r[a->rd]; in trans_LDS()
1592 tcg_gen_ori_tl(addr, addr, a->imm); in trans_LDS()
1608 * area has to be changed. The X-pointer Register can either be left unchanged
1609 * by the operation, or it can be post-incremented or predecremented. These
1611 * Pointer usage of the X-pointer Register. Note that only the low byte of the
1612 * X-pointer is updated in devices with no more than 256 bytes data space. For
1616 * memory, and the increment/decrement is added to the entire 24-bit address on
1625 TCGv Rd = cpu_r[a->rd]; in trans_LDX1()
1634 TCGv Rd = cpu_r[a->rd]; in trans_LDX2()
1646 TCGv Rd = cpu_r[a->rd]; in trans_LDX3()
1649 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ in trans_LDX3()
1665 * RAMPY in register in the I/O area has to be changed. The Y-pointer Register
1666 * can either be left unchanged by the operation, or it can be post-incremented
1668 * arrays, tables, and Stack Pointer usage of the Y-pointer Register. Note that
1669 * only the low byte of the Y-pointer is updated in devices with no more than
1674 * is added to the entire 24-bit address on such devices. Not all variants of
1682 TCGv Rd = cpu_r[a->rd]; in trans_LDY2()
1694 TCGv Rd = cpu_r[a->rd]; in trans_LDY3()
1697 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ in trans_LDY3()
1705 TCGv Rd = cpu_r[a->rd]; in trans_LDDY()
1708 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ in trans_LDDY()
1723 * RAMPZ in register in the I/O area has to be changed. The Z-pointer Register
1724 * can either be left unchanged by the operation, or it can be post-incremented
1726 * usage of the Z-pointer Register, however because the Z-pointer Register can
1728 * is often more convenient to use the X or Y-pointer as a dedicated Stack
1729 * Pointer. Note that only the low byte of the Z-pointer is updated in devices
1734 * increment/decrement/displacement is added to the entire 24-bit address on
1739 * space. For using the Z-pointer for table lookup in Program memory see the
1744 TCGv Rd = cpu_r[a->rd]; in trans_LDZ2()
1756 TCGv Rd = cpu_r[a->rd]; in trans_LDZ3()
1759 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ in trans_LDZ3()
1768 TCGv Rd = cpu_r[a->rd]; in trans_LDDZ()
1771 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ in trans_LDDZ()
1781 * A 16-bit address must be supplied. Memory access is limited to the current
1790 TCGv Rd = cpu_r[a->rd]; in trans_STS()
1796 tcg_gen_ori_tl(addr, addr, a->imm); in trans_STS()
1812 * The X-pointer Register can either be left unchanged by the operation, or it
1813 * can be post-incremented or pre-decremented. These features are especially
1815 * X-pointer Register. Note that only the low byte of the X-pointer is updated
1820 * decrement is added to the entire 24-bit address on such devices.
1824 TCGv Rd = cpu_r[a->rr]; in trans_STX1()
1833 TCGv Rd = cpu_r[a->rr]; in trans_STX2()
1844 TCGv Rd = cpu_r[a->rr]; in trans_STX3()
1847 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ in trans_STX3()
1865 * The Y-pointer Register can either be left unchanged by the operation, or it
1866 * can be post-incremented or pre-decremented. These features are especially
1867 * suited for accessing arrays, tables, and Stack Pointer usage of the Y-pointer
1868 * Register. Note that only the low byte of the Y-pointer is updated in devices
1873 * decrement / displacement is added to the entire 24-bit address on such
1878 TCGv Rd = cpu_r[a->rd]; in trans_STY2()
1889 TCGv Rd = cpu_r[a->rd]; in trans_STY3()
1892 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ in trans_STY3()
1900 TCGv Rd = cpu_r[a->rd]; in trans_STDY()
1903 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ in trans_STDY()
1920 * The Y-pointer Register can either be left unchanged by the operation, or it
1921 * can be post-incremented or pre-decremented. These features are especially
1922 * suited for accessing arrays, tables, and Stack Pointer usage of the Y-pointer
1923 * Register. Note that only the low byte of the Y-pointer is updated in devices
1928 * decrement / displacement is added to the entire 24-bit address on such
1933 TCGv Rd = cpu_r[a->rd]; in trans_STZ2()
1945 TCGv Rd = cpu_r[a->rd]; in trans_STZ3()
1948 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ in trans_STZ3()
1957 TCGv Rd = cpu_r[a->rd]; in trans_STDZ()
1960 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ in trans_STDZ()
1966 * Loads one byte pointed to by the Z-register into the destination
1969 * 16-bit words while the Z-pointer is a byte address. Thus, the least
1970 * significant bit of the Z-pointer selects either low byte (ZLSB = 0) or high
1976 * Devices with Self-Programming capability can use the LPM instruction to read
2002 TCGv Rd = cpu_r[a->rd]; in trans_LPM2()
2019 TCGv Rd = cpu_r[a->rd]; in trans_LPMX()
2035 * Loads one byte pointed to by the Z-register and the RAMPZ Register in
2038 * constant data fetch. The Program memory is organized in 16-bit words while
2039 * the Z-pointer is a byte address. Thus, the least significant bit of the
2040 * Z-pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = 1). This
2041 * instruction can address the entire Program memory space. The Z-pointer
2043 * incremented. The incrementation applies to the entire 24-bit concatenation
2044 * of the RAMPZ and Z-pointer Registers.
2046 * Devices with Self-Programming capability can use the ELPM instruction to
2068 TCGv Rd = cpu_r[a->rd]; in trans_ELPM2()
2081 TCGv Rd = cpu_r[a->rd]; in trans_ELPMX()
2097 * Z-register are used as page address. When writing the Program memory, the
2098 * RAMPZ and Z-register are used as page or word address, and the R1:R0
2136 TCGv Rd = cpu_r[a->rd]; in trans_IN()
2138 gen_inb(ctx, Rd, a->imm); in trans_IN()
2148 TCGv Rd = cpu_r[a->rd]; in trans_OUT()
2150 gen_outb(ctx, Rd, a->imm); in trans_OUT()
2156 * Stack Pointer is post-decremented by 1 after the PUSH. This instruction is
2162 TCGv Rd = cpu_r[a->rd]; in trans_PUSH()
2172 * Pointer is pre-incremented by 1 before the POP. This instruction is not
2186 TCGv Rd = cpu_r[a->rd]; in trans_POP()
2202 * The Z-pointer Register is left unchanged by the operation. This instruction
2211 TCGv Rd = cpu_r[a->rd]; in trans_XCH()
2229 * The Z-pointer Register is left unchanged by the operation. This instruction
2238 TCGv Rr = cpu_r[a->rd]; in trans_LAS()
2259 * The Z-pointer Register is left unchanged by the operation. This instruction
2268 TCGv Rr = cpu_r[a->rd]; in trans_LAC()
2274 tcg_gen_andc_tl(t1, t0, Rr); /* t1 = t0 & (0xff - Rr) = t0 & ~Rr */ in trans_LAC()
2289 * The Z-pointer Register is left unchanged by the operation. This instruction
2298 TCGv Rd = cpu_r[a->rd]; in trans_LAT()
2311 * Bit and Bit-test Instructions
2328 TCGv Rd = cpu_r[a->rd]; in trans_LSR()
2345 * with ASR, effectively divides multi-byte signed values by two. Combined with
2346 * LSR it effectively divides multi-byte unsigned values by two. The Carry Flag
2351 TCGv Rd = cpu_r[a->rd]; in trans_ROR()
2376 TCGv Rd = cpu_r[a->rd]; in trans_ASR()
2397 TCGv Rd = cpu_r[a->rd]; in trans_SWAP()
2411 * the lower 32 I/O Registers -- addresses 0-31.
2417 gen_inb(ctx, data, a->reg); in trans_SBI()
2418 tcg_gen_ori_tl(data, data, 1 << a->bit); in trans_SBI()
2419 gen_outb(ctx, data, a->reg); in trans_SBI()
2425 * the lower 32 I/O Registers -- addresses 0-31.
2431 gen_inb(ctx, data, a->reg); in trans_CBI()
2432 tcg_gen_andi_tl(data, data, ~(1 << a->bit)); in trans_CBI()
2433 gen_outb(ctx, data, a->reg); in trans_CBI()
2442 TCGv Rd = cpu_r[a->rd]; in trans_BST()
2444 tcg_gen_andi_tl(cpu_Tf, Rd, 1 << a->bit); in trans_BST()
2445 tcg_gen_shri_tl(cpu_Tf, cpu_Tf, a->bit); in trans_BST()
2455 TCGv Rd = cpu_r[a->rd]; in trans_BLD()
2458 tcg_gen_andi_tl(Rd, Rd, ~(1u << a->bit)); /* clear bit */ in trans_BLD()
2459 tcg_gen_shli_tl(t1, cpu_Tf, a->bit); /* create mask */ in trans_BLD()
2469 switch (a->bit) { in trans_BSET()
2504 switch (a->bit) { in trans_BCLR()
2539 * The BREAK instruction is used by the On-chip Debug system, and is
2541 * executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip
2555 tcg_gen_movi_tl(cpu_pc, ctx->npc - 1); in trans_BREAK()
2557 ctx->base.is_jmp = DISAS_EXIT; in trans_BREAK()
2583 ctx->base.is_jmp = DISAS_NORETURN; in trans_SLEEP()
2602 * - translate()
2603 * - canonicalize_skip()
2604 * - translate_code()
2605 * - restore_state_to_opc()
2614 ctx->base.is_jmp = DISAS_NORETURN; in translate()
2621 switch (ctx->skip_cond) { in canonicalize_skip()
2635 if (ctx->skip_var1 == NULL) { in canonicalize_skip()
2636 tcg_gen_mov_tl(cpu_skip, ctx->skip_var0); in canonicalize_skip()
2638 tcg_gen_xor_tl(cpu_skip, ctx->skip_var0, ctx->skip_var1); in canonicalize_skip()
2639 ctx->skip_var1 = NULL; in canonicalize_skip()
2645 if (ctx->skip_var1 == NULL) { in canonicalize_skip()
2646 tcg_gen_setcondi_tl(ctx->skip_cond, cpu_skip, ctx->skip_var0, 0); in canonicalize_skip()
2648 tcg_gen_setcond_tl(ctx->skip_cond, cpu_skip, in canonicalize_skip()
2649 ctx->skip_var0, ctx->skip_var1); in canonicalize_skip()
2650 ctx->skip_var1 = NULL; in canonicalize_skip()
2652 ctx->skip_cond = TCG_COND_NE; in canonicalize_skip()
2655 ctx->skip_var0 = cpu_skip; in canonicalize_skip()
2662 uint32_t tb_flags = ctx->base.tb->flags; in avr_tr_init_disas_context()
2664 ctx->cs = cs; in avr_tr_init_disas_context()
2665 ctx->env = cpu_env(cs); in avr_tr_init_disas_context()
2666 ctx->npc = ctx->base.pc_first / 2; in avr_tr_init_disas_context()
2668 ctx->skip_cond = TCG_COND_NEVER; in avr_tr_init_disas_context()
2670 ctx->skip_cond = TCG_COND_ALWAYS; in avr_tr_init_disas_context()
2671 ctx->skip_var0 = cpu_skip; in avr_tr_init_disas_context()
2679 ctx->base.max_insns = 1; in avr_tr_init_disas_context()
2691 tcg_gen_insn_start(ctx->npc); in avr_tr_insn_start()
2700 if (ctx->skip_cond != TCG_COND_NEVER) { in avr_tr_translate_insn()
2702 if (ctx->skip_var0 == cpu_skip) { in avr_tr_translate_insn()
2705 * This ensures that cpu_skip is non-zero after the label in avr_tr_translate_insn()
2708 ctx->skip_var0 = tcg_temp_new(); in avr_tr_translate_insn()
2709 tcg_gen_mov_tl(ctx->skip_var0, cpu_skip); in avr_tr_translate_insn()
2712 if (ctx->skip_var1 == NULL) { in avr_tr_translate_insn()
2713 tcg_gen_brcondi_tl(ctx->skip_cond, ctx->skip_var0, 0, skip_label); in avr_tr_translate_insn()
2715 tcg_gen_brcond_tl(ctx->skip_cond, ctx->skip_var0, in avr_tr_translate_insn()
2716 ctx->skip_var1, skip_label); in avr_tr_translate_insn()
2717 ctx->skip_var1 = NULL; in avr_tr_translate_insn()
2719 ctx->skip_cond = TCG_COND_NEVER; in avr_tr_translate_insn()
2720 ctx->skip_var0 = NULL; in avr_tr_translate_insn()
2725 ctx->base.pc_next = ctx->npc * 2; in avr_tr_translate_insn()
2731 switch (ctx->base.is_jmp) { in avr_tr_translate_insn()
2733 ctx->base.is_jmp = DISAS_CHAIN; in avr_tr_translate_insn()
2736 if (ctx->base.tb->flags & TB_FLAGS_SKIP) { in avr_tr_translate_insn()
2737 ctx->base.is_jmp = DISAS_TOO_MANY; in avr_tr_translate_insn()
2745 if (ctx->base.is_jmp == DISAS_NEXT) { in avr_tr_translate_insn()
2746 target_ulong page_first = ctx->base.pc_first & TARGET_PAGE_MASK; in avr_tr_translate_insn()
2748 if ((ctx->base.pc_next - page_first) >= TARGET_PAGE_SIZE - 4) { in avr_tr_translate_insn()
2749 ctx->base.is_jmp = DISAS_TOO_MANY; in avr_tr_translate_insn()
2759 * Because we disable interrupts while env->skip is set, in avr_tr_tb_stop()
2760 * we must return to the main loop to re-evaluate afterward. in avr_tr_tb_stop()
2762 bool force_exit = ctx->base.tb->flags & TB_FLAGS_SKIP; in avr_tr_tb_stop()
2764 switch (ctx->base.is_jmp) { in avr_tr_tb_stop()
2773 gen_goto_tb(ctx, 1, ctx->npc); in avr_tr_tb_stop()
2776 tcg_gen_movi_tl(cpu_pc, ctx->npc); in avr_tr_tb_stop()