arm/tcg/translate.h

198 static inline int negate(DisasContext *s, int x)
203 static inline int plus_1(DisasContext *s, int x)
208 static inline int plus_2(DisasContext *s, int x)
213 static inline int plus_8(DisasContext *s, int x)
218 static inline int plus_12(DisasContext *s, int x)
223 static inline int times_2(DisasContext *s, int x)
228 static inline int times_4(DisasContext *s, int x)
233 static inline int times_8(DisasContext *s, int x)
238 static inline int times_2_plus_1(DisasContext *s, int x)
243 static inline int rsub_64(DisasContext *s, int x)
248 static inline int rsub_32(DisasContext *s, int x)
253 static inline int rsub_16(DisasContext *s, int x)
258 static inline int rsub_8(DisasContext *s, int x)
263 static inline int shl_12(DisasContext *s, int x)
268 static inline int xor_2(DisasContext *s, int x)
273 static inline int neon_3same_fp_size(DisasContext *s, int x)
284 static inline int get_mem_index(DisasContext *s)
286     return arm_to_core_mmu_idx(s->mmu_idx);
289 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
298     assert(!s->insn_start_updated);
299     s->insn_start_updated = true;
300     tcg_set_insn_start_param(s->base.insn_start, 2, syn);
303 static inline int curr_insn_len(DisasContext *s)
305     return s->base.pc_next - s->pc_curr;
340 void gen_a64_update_pc(DisasContext *s, target_long diff);
347 static inline void gen_a64_update_pc(DisasContext *s, target_long diff)
356 void unallocated_encoding(DisasContext *s);
358 void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp,
360 void gen_exception_insn(DisasContext *s, target_long pc_diff,
399 static inline void gen_ss_advance(DisasContext *s)
401     if (s->ss_active) {
402         s->pstate_ss = 0;
408 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
422 static inline void gen_vfp_absh(TCGv_i32 d, TCGv_i32 s)
424     tcg_gen_andi_i32(d, s, INT16_MAX);
427 static inline void gen_vfp_abss(TCGv_i32 d, TCGv_i32 s)
429     tcg_gen_andi_i32(d, s, INT32_MAX);
432 static inline void gen_vfp_absd(TCGv_i64 d, TCGv_i64 s)
434     tcg_gen_andi_i64(d, s, INT64_MAX);
437 static inline void gen_vfp_negh(TCGv_i32 d, TCGv_i32 s)
439     tcg_gen_xori_i32(d, s, 1u << 15);
442 static inline void gen_vfp_negs(TCGv_i32 d, TCGv_i32 s)
444     tcg_gen_xori_i32(d, s, 1u << 31);
447 static inline void gen_vfp_negd(TCGv_i64 d, TCGv_i64 s)
449     tcg_gen_xori_i64(d, s, 1ull << 63);
704  * @s: DisasContext
719 static inline MemOp finalize_memop_atom(DisasContext *s, MemOp opc, MemOp atom)
721     if (s->align_mem && !(opc & MO_AMASK)) {
724     return opc | atom | s->be_data;
729  * @s: DisasContext
734 static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
736     MemOp atom = s->lse2 ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN;
737     return finalize_memop_atom(s, opc, atom);
742  * @s: DisasContext
748 static inline MemOp finalize_memop_pair(DisasContext *s, MemOp opc)
750     MemOp atom = s->lse2 ? MO_ATOM_WITHIN16_PAIR : MO_ATOM_IFALIGN_PAIR;
751     return finalize_memop_atom(s, opc, atom);
756  * @s: DisasContext
761 static inline MemOp finalize_memop_asimd(DisasContext *s, MemOp opc)
773         return finalize_memop_atom(s, opc, MO_ATOM_IFALIGN_PAIR);
775     return finalize_memop(s, opc);
799 static inline DisasLabel gen_disas_label(DisasContext *s)
803         .pc_save = s->pc_save,
811 static inline void set_disas_label(DisasContext *s, DisasLabel l)
814     s->pc_save = l.pc_save;
846     static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
847     { return FUNC(s, __VA_ARGS__); }
849     static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
850     { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
853     static bool trans_##NAME(DisasContext *s, arg_##NAME *a)      \
855         s->is_nonstreaming = true;                                \
856         return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__);  \