Lines Matching defs:val

1727         int val = (1 << 15) | (1 << a->esz);
1729         /* Write val to the first uint64_t; clear all of the rest. */
1731                              8, size_for_gvec(pred_full_reg_size(s)), val);
1797 static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
1808         tcg_gen_sub_i64(reg, reg, val);
1812         tcg_gen_add_i64(reg, reg, val);
1819 static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
1826             tcg_gen_sub_i64(t0, reg, val);
1828             tcg_gen_movcond_i64(TCG_COND_LTU, reg, reg, val, t2, t0);
1830             tcg_gen_add_i64(t0, reg, val);
1838             tcg_gen_xor_i64(t0, reg, val);
1839             tcg_gen_sub_i64(t1, reg, val);
1849             tcg_gen_xor_i64(t0, reg, val);
1850             tcg_gen_add_i64(reg, reg, val);
1851             tcg_gen_xor_i64(t1, reg, val);
1864                               TCGv_i64 val, bool u, bool d)
1880         tcg_gen_extrl_i64_i32(t32, val);
1893         tcg_gen_extrl_i64_i32(t32, val);
1907             tcg_gen_neg_i64(t64, val);
1909             tcg_gen_mov_i64(t64, val);
1921                 gen_helper_sve_uqsubi_d(dptr, nptr, val, desc);
1923                 gen_helper_sve_uqaddi_d(dptr, nptr, val, desc);
1927             tcg_gen_neg_i64(t64, val);
1930             gen_helper_sve_sqaddi_d(dptr, nptr, val, desc);
2104                      TCGv_i64 val)
2121     fns[esz](t_zd, t_zn, t_pg, val, desc);
2322 static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val)
2337     fns[a->esz](t_zd, t_zn, val, desc);
2924         TCGv_i64 val = do_last_scalar(s, a->esz, a->pg, a->rn, before);
2925         write_fp_dreg(s, a->rd, val);
2937         TCGv_i64 val = do_last_scalar(s, a->esz, a->pg, a->rn, before);
2938         tcg_gen_mov_i64(cpu_reg(s, a->rd), val);
3207 static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg)
3214         tcg_gen_ld_i64(val, tcg_env, pred_full_reg_offset(s, pn));
3218             tcg_gen_and_i64(val, val, g);
3225         tcg_gen_andi_i64(val, val, pred_esz_masks[esz] & psz_mask);
3227         tcg_gen_ctpop_i64(val, val);
3239         gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc));
3291         TCGv_i64 val = tcg_temp_new_i64();
3293         do_cntp(s, val, a->esz, a->pg, a->pg);
3295             tcg_gen_sub_i64(reg, reg, val);
3297             tcg_gen_add_i64(reg, reg, val);
3310         TCGv_i64 val = tcg_temp_new_i64();
3313         do_cntp(s, val, a->esz, a->pg, a->pg);
3315                 vec_full_reg_offset(s, a->rn), val, vsz, vsz);
3327         TCGv_i64 val = tcg_temp_new_i64();
3329         do_cntp(s, val, a->esz, a->pg, a->pg);
3330         do_sat_addsub_32(reg, val, a->u, a->d);
3342         TCGv_i64 val = tcg_temp_new_i64();
3344         do_cntp(s, val, a->esz, a->pg, a->pg);
3345         do_sat_addsub_64(reg, val, a->u, a->d);
3356         TCGv_i64 val = tcg_temp_new_i64();
3357         do_cntp(s, val, a->esz, a->pg, a->pg);
3358         do_sat_addsub_vec(s, a->esz, a->rd, a->rn, val, a->u, a->d);