arm/tcg/a64.decode

97 ### Data Processing - Immediate
99 # PC-rel addressing
252   NOP           1101 0101 0000 0011 0010 ---- --- 11111
261 CLREX           1101 0101 0000 0011 0011 ---- 010 11111
262 DSB_DMB         1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
265 DSB_nXS         1101 0101 0000 0011 0011 -- 10 001 11111
266 ISB             1101 0101 0000 0011 0011 ---- 110 11111
292 # to hand-decode it.
330 CASP            0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2
332 CAS             sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5
345 NOP             11 011 0 00 ------------------- -----
350 # STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches
364 # STP and LDP: post-indexed
390 # STP and LDP: pre-indexed
459 # PRFM : prefetch memory: a no-op for QEMU
460 NOP             11 111 0 00 10 0 --------- 00 ----- -----
495 NOP             11 111 0 01 10 ------------ ----- -----
517 NOP             11 111 0 00 10 1 ----- -1- - 10 ----- -----
557 # The 4-bit opcode in [15:12] encodes repeat count and structure elements
638 # indicate whether memory accesses should be unpriv or non-temporal.
639 # We don't distinguish temporal and non-temporal accesses, but we
670 ### Data Processing (register)
672 # Data Processing (2-source)
701 # Data Processing (1-source)
784 # Data Processing (3-source)
809 ### Cryptographic three-register SHA
819 ### Cryptographic two-register SHA
825 ### Cryptographic three-register SHA512
835 ### Cryptographic two-register SHA512
840 ### Cryptographic four-register
846 ### Cryptographic three-register, imm2
1283 # Floating-point conditional select
1287 # Floating-point data-processing (3 source)
1336 # Conversion between floating-point and fixed-point (general register)
1357 # Conversion between floating-point and integer (general register)
1384 # Move to/from upper half of 128-bit
1388 # Half-precision allows both sf=0 and sf=1 with identical results
1389 FMOV_xh         - 0011110 11 100110 000000 ..... .....  @rr
1390 FMOV_hx         - 0011110 11 100111 000000 ..... .....  @rr
1392 # Floating-point data processing (1 source)
1421 # Floating-point Immediate
1425 # Floating-point Compare
1429 # Floating-point Conditional Compare
1437 # Right shifts are encoded as N - shift, where N is the element size in bits.
1640 # Advanced SIMD scalar two-register miscellaneous
1745 # Advanced SIMD two-register miscellaneous