32      * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
39      * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
50      *    stage 1 is Secure; in that case the only possibilities for
51      *    the ptw read are Secure and NonSecure, and the in_ptw_idx
168  * Secure IPA or a NonSecure IPA, which we know from whether this is
170  * If this is the Secure EL1&0 regime we need to check the NSW and SW bits.
182      * never has a secure EL2. (AArch32 ATS12NSO[UP][RW] allow EL3 to do  in ptw_idx_for_stage_2()
309         .secure = true,  in granule_protection_check()
374      * GPC Priority 2: Secure, Realm or Root address exceeds PPS.  in granule_protection_check()
534          * The only exception is when stage 1 is Secure; in that case  in S2_security_space()
535          * the ptw read might be to the Secure or the NonSecure space  in S2_security_space()
555      * For stage 2 faults in Secure EL22, S1NS indicates  in fault_s1ns()
556      * whether the faulting IPA is in the Secure or NonSecure  in fault_s1ns()
671             .secure = arm_space_is_secure(ptw->out_space),  in arm_ldl_ptw()
717             .secure = arm_space_is_secure(ptw->out_space),  in arm_ldq_ptw()
749             .secure = arm_space_is_secure(ptw->out_space),  in arm_casq_ptw()
1219          * the CPU doesn't support TZ or this is a non-secure translation  in get_phys_addr_v6()
1220          * regime, because the output space will already be non-secure.  in get_phys_addr_v6()
1253     result->f.attrs.secure = arm_space_is_secure(out_space);  in get_phys_addr_v6()
1844      * the table address space and the output space from Secure to  in get_phys_addr_lpae()
1853          * Assert the relative order of the secure/non-secure indexes.  in get_phys_addr_lpae()
2038                  * NS changes the output to non-secure space.  in get_phys_addr_lpae()
2151     result->f.attrs.secure = arm_space_is_secure(out_space);  in get_phys_addr_lpae()
2361     bool secure = arm_space_is_secure(ptw->in_space);  in get_phys_addr_pmsav7()  local
2463             if (!pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) {  in get_phys_addr_pmsav7()
2544                              uint32_t secure)  in regime_rbar()  argument
2549         return env->pmsav8.rbar[secure];  in regime_rbar()
2554                              uint32_t secure)  in regime_rlar()  argument
2559         return env->pmsav8.rlar[secure];  in regime_rlar()
2565                        bool secure, GetPhysAddrResult *result,  in pmsav8_mpu_lookup()  argument
2611     if (regime_translation_disabled(env, mmu_idx, arm_secure_to_space(secure))) {  in pmsav8_mpu_lookup()
2617         if (pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) {  in pmsav8_mpu_lookup()
2637             uint32_t base = regime_rbar(env, mmu_idx, secure)[n] & ~bitmask;  in pmsav8_mpu_lookup()
2638             uint32_t limit = regime_rlar(env, mmu_idx, secure)[n] | bitmask;  in pmsav8_mpu_lookup()
2640             if (!(regime_rlar(env, mmu_idx, secure)[n] & 0x1)) {  in pmsav8_mpu_lookup()
2698         uint32_t matched_rbar = regime_rbar(env, mmu_idx, secure)[matchregion];  in pmsav8_mpu_lookup()
2699         uint32_t matched_rlar = regime_rlar(env, mmu_idx, secure)[matchregion];  in pmsav8_mpu_lookup()
2830                          * as Secure, not NS-Callable, with no valid region  in v8m_security_lookup()
2890     bool secure = arm_space_is_secure(ptw->in_space);  in get_phys_addr_pmsav8()  local
2895                             secure, &sattrs);  in get_phys_addr_pmsav8()
2915             if (sattrs.ns != !secure) {  in get_phys_addr_pmsav8()
2930              * might downgrade a secure access to nonsecure.  in get_phys_addr_pmsav8()
2933                 result->f.attrs.secure = false;  in get_phys_addr_pmsav8()
2935             } else if (!secure) {  in get_phys_addr_pmsav8()
2955     ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure,  in get_phys_addr_pmsav8()
3300     ipa_secure = result->f.attrs.secure;  in get_phys_addr_twostage()
3370      * Check if IPA translates to secure or non-secure PA space.  in get_phys_addr_twostage()
3374         result->f.attrs.secure =  in get_phys_addr_twostage()
3378         result->f.attrs.space = arm_secure_to_space(result->f.attrs.secure);  in get_phys_addr_twostage()
3394      * The page table entries may downgrade Secure to NonSecure, but  in get_phys_addr_nogpc()
3396      * to Secure or Realm.  in get_phys_addr_nogpc()
3399     result->f.attrs.secure = arm_space_is_secure(ptw->in_space);  in get_phys_addr_nogpc()
3415          * Secure has both S and NS IPA and starts with Stage2_S.  in get_phys_addr_nogpc()
3426          * the Secure EL2&0 regime.  in get_phys_addr_nogpc()
3574          * For Secure EL2, we need this index to be NonSecure;  in arm_mmu_idx_to_security_space()