Lines Matching full:fi
79 ARMMMUFaultInfo *fi);
85 ARMMMUFaultInfo *fi);
306 ARMMMUFaultInfo *fi) in granule_protection_check() argument
478 fi->gpcf = GPCF_Fail; in granule_protection_check()
481 fi->gpcf = GPCF_EABT; in granule_protection_check()
484 fi->gpcf = GPCF_AddressSize; in granule_protection_check()
487 fi->gpcf = GPCF_Walk; in granule_protection_check()
489 fi->level = level; in granule_protection_check()
490 fi->paddr = paddress; in granule_protection_check()
491 fi->paddr_space = pspace; in granule_protection_check()
565 hwaddr addr, ARMMMUFaultInfo *fi) in S1_ptw_translate() argument
587 if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, 0, &s2, fi)) { in S1_ptw_translate()
601 env->tlb_fi = fi; in S1_ptw_translate()
627 fi->type = ARMFault_Permission; in S1_ptw_translate()
628 fi->s2addr = addr; in S1_ptw_translate()
629 fi->stage2 = true; in S1_ptw_translate()
630 fi->s1ptw = true; in S1_ptw_translate()
631 fi->s1ns = fault_s1ns(ptw->in_space, s2_mmu_idx); in S1_ptw_translate()
640 assert(fi->type != ARMFault_None); in S1_ptw_translate()
641 if (fi->type == ARMFault_GPCFOnOutput) { in S1_ptw_translate()
642 fi->type = ARMFault_GPCFOnWalk; in S1_ptw_translate()
644 fi->s2addr = addr; in S1_ptw_translate()
645 fi->stage2 = regime_is_stage2(s2_mmu_idx); in S1_ptw_translate()
646 fi->s1ptw = fi->stage2; in S1_ptw_translate()
647 fi->s1ns = fault_s1ns(ptw->in_space, s2_mmu_idx); in S1_ptw_translate()
653 ARMMMUFaultInfo *fi) in arm_ldl_ptw() argument
682 fi->type = ARMFault_SyncExternalOnWalk; in arm_ldl_ptw()
683 fi->ea = arm_extabort_type(result); in arm_ldl_ptw()
691 ARMMMUFaultInfo *fi) in arm_ldq_ptw() argument
728 fi->type = ARMFault_SyncExternalOnWalk; in arm_ldq_ptw()
729 fi->ea = arm_extabort_type(result); in arm_ldq_ptw()
738 ARMMMUFaultInfo *fi) in arm_casq_ptw() argument
761 fi->type = ARMFault_SyncExternalOnWalk; in arm_casq_ptw()
762 fi->ea = arm_extabort_type(result); in arm_casq_ptw()
771 fi->type = ARMFault_SyncExternalOnWalk; in arm_casq_ptw()
772 fi->ea = arm_extabort_type(result); in arm_casq_ptw()
783 fi->type = ARMFault_SyncExternalOnWalk; in arm_casq_ptw()
784 fi->ea = arm_extabort_type(result); in arm_casq_ptw()
793 fi->type = ARMFault_SyncExternalOnWalk; in arm_casq_ptw()
794 fi->ea = arm_extabort_type(result); in arm_casq_ptw()
816 env->tlb_fi = fi; in arm_casq_ptw()
830 assert(fi->type != ARMFault_None); in arm_casq_ptw()
831 fi->s2addr = ptw->out_virt; in arm_casq_ptw()
832 fi->stage2 = true; in arm_casq_ptw()
833 fi->s1ptw = true; in arm_casq_ptw()
834 fi->s1ns = fault_s1ns(ptw->in_space, ptw->in_ptw_idx); in arm_casq_ptw()
983 GetPhysAddrResult *result, ARMMMUFaultInfo *fi) in get_phys_addr_v5() argument
999 fi->type = ARMFault_Translation; in get_phys_addr_v5()
1002 if (!S1_ptw_translate(env, ptw, table, fi)) { in get_phys_addr_v5()
1005 desc = arm_ldl_ptw(env, ptw, fi); in get_phys_addr_v5()
1006 if (fi->type != ARMFault_None) { in get_phys_addr_v5()
1019 fi->type = ARMFault_Translation; in get_phys_addr_v5()
1026 fi->type = ARMFault_Domain; in get_phys_addr_v5()
1043 if (!S1_ptw_translate(env, ptw, table, fi)) { in get_phys_addr_v5()
1046 desc = arm_ldl_ptw(env, ptw, fi); in get_phys_addr_v5()
1047 if (fi->type != ARMFault_None) { in get_phys_addr_v5()
1052 fi->type = ARMFault_Translation; in get_phys_addr_v5()
1076 fi->type = ARMFault_Translation; in get_phys_addr_v5()
1094 fi->type = ARMFault_Permission; in get_phys_addr_v5()
1100 fi->domain = domain; in get_phys_addr_v5()
1101 fi->level = level; in get_phys_addr_v5()
1107 GetPhysAddrResult *result, ARMMMUFaultInfo *fi) in get_phys_addr_v6() argument
1129 fi->type = ARMFault_Translation; in get_phys_addr_v6()
1132 if (!S1_ptw_translate(env, ptw, table, fi)) { in get_phys_addr_v6()
1135 desc = arm_ldl_ptw(env, ptw, fi); in get_phys_addr_v6()
1136 if (fi->type != ARMFault_None) { in get_phys_addr_v6()
1144 fi->type = ARMFault_Translation; in get_phys_addr_v6()
1162 fi->type = ARMFault_Domain; in get_phys_addr_v6()
1188 if (!S1_ptw_translate(env, ptw, table, fi)) { in get_phys_addr_v6()
1191 desc = arm_ldl_ptw(env, ptw, fi); in get_phys_addr_v6()
1192 if (fi->type != ARMFault_None) { in get_phys_addr_v6()
1198 fi->type = ARMFault_Translation; in get_phys_addr_v6()
1234 fi->type = ARMFault_AccessFlag; in get_phys_addr_v6()
1248 fi->type = ARMFault_Permission; in get_phys_addr_v6()
1257 fi->domain = domain; in get_phys_addr_v6()
1258 fi->level = level; in get_phys_addr_v6()
1649 * @fi: set to fault info if the translation fails
1654 GetPhysAddrResult *result, ARMMMUFaultInfo *fi) in get_phys_addr_lpae() argument
1810 fi->type = ARMFault_AddressSize; in get_phys_addr_lpae()
1861 if (!S1_ptw_translate(env, ptw, descaddr, fi)) { in get_phys_addr_lpae()
1864 descriptor = arm_ldq_ptw(env, ptw, fi); in get_phys_addr_lpae()
1865 if (fi->type != ARMFault_None) { in get_phys_addr_lpae()
1893 fi->type = ARMFault_AddressSize; in get_phys_addr_lpae()
1935 fi->type = ARMFault_AccessFlag; in get_phys_addr_lpae()
2118 fi->type = ARMFault_Alignment; in get_phys_addr_lpae()
2127 fi->type = ARMFault_Permission; in get_phys_addr_lpae()
2133 new_descriptor = arm_casq_ptw(env, descriptor, new_descriptor, ptw, fi); in get_phys_addr_lpae()
2134 if (fi->type != ARMFault_None) { in get_phys_addr_lpae()
2169 fi->type = ARMFault_Translation; in get_phys_addr_lpae()
2171 if (fi->s1ptw) { in get_phys_addr_lpae()
2172 /* Retain the existing stage 2 fi->level */ in get_phys_addr_lpae()
2173 assert(fi->stage2); in get_phys_addr_lpae()
2175 fi->level = level; in get_phys_addr_lpae()
2176 fi->stage2 = regime_is_stage2(mmu_idx); in get_phys_addr_lpae()
2178 fi->s1ns = fault_s1ns(ptw->in_space, mmu_idx); in get_phys_addr_lpae()
2187 ARMMMUFaultInfo *fi) in get_phys_addr_pmsav5() argument
2217 fi->type = ARMFault_Background; in get_phys_addr_pmsav5()
2229 fi->type = ARMFault_Permission; in get_phys_addr_pmsav5()
2230 fi->level = 1; in get_phys_addr_pmsav5()
2234 fi->type = ARMFault_Permission; in get_phys_addr_pmsav5()
2235 fi->level = 1; in get_phys_addr_pmsav5()
2251 fi->type = ARMFault_Permission; in get_phys_addr_pmsav5()
2252 fi->level = 1; in get_phys_addr_pmsav5()
2262 fi->type = ARMFault_Permission; in get_phys_addr_pmsav5()
2263 fi->level = 1; in get_phys_addr_pmsav5()
2355 ARMMMUFaultInfo *fi) in get_phys_addr_pmsav7() argument
2465 fi->type = ARMFault_Background; in get_phys_addr_pmsav7()
2538 fi->type = ARMFault_Permission; in get_phys_addr_pmsav7()
2539 fi->level = 1; in get_phys_addr_pmsav7()
2566 ARMMMUFaultInfo *fi, uint32_t *mregion) in pmsav8_mpu_lookup() argument
2601 fi->stage2 = true; in pmsav8_mpu_lookup()
2626 fi->level = 0; in pmsav8_mpu_lookup()
2673 fi->type = ARMFault_Permission; in pmsav8_mpu_lookup()
2675 fi->level = 1; in pmsav8_mpu_lookup()
2687 fi->type = ARMFault_Background; in pmsav8_mpu_lookup()
2689 fi->type = ARMFault_Permission; in pmsav8_mpu_lookup()
2749 fi->type = ARMFault_Permission; in pmsav8_mpu_lookup()
2751 fi->level = 1; in pmsav8_mpu_lookup()
2886 ARMMMUFaultInfo *fi) in get_phys_addr_pmsav8() argument
2917 fi->type = ARMFault_QEMU_NSCExec; in get_phys_addr_pmsav8()
2919 fi->type = ARMFault_QEMU_SFault; in get_phys_addr_pmsav8()
2946 fi->type = ARMFault_QEMU_SFault; in get_phys_addr_pmsav8()
2956 result, fi, NULL); in get_phys_addr_pmsav8()
3198 ARMMMUFaultInfo *fi) in get_phys_addr_disabled() argument
3229 fi->type = ARMFault_AddressSize; in get_phys_addr_disabled()
3230 fi->level = 0; in get_phys_addr_disabled()
3231 fi->stage2 = false; in get_phys_addr_disabled()
3281 ARMMMUFaultInfo *fi) in get_phys_addr_twostage() argument
3292 memop, result, fi); in get_phys_addr_twostage()
3319 memop, result, fi); in get_phys_addr_twostage()
3320 fi->s2addr = ipa; in get_phys_addr_twostage()
3388 ARMMMUFaultInfo *fi) in get_phys_addr_nogpc() argument
3408 result, fi); in get_phys_addr_nogpc()
3449 memop, result, fi); in get_phys_addr_nogpc()
3481 result, fi); in get_phys_addr_nogpc()
3485 result, fi); in get_phys_addr_nogpc()
3489 result, fi); in get_phys_addr_nogpc()
3508 result, fi); in get_phys_addr_nogpc()
3513 memop, result, fi); in get_phys_addr_nogpc()
3516 return get_phys_addr_v6(env, ptw, address, access_type, result, fi); in get_phys_addr_nogpc()
3518 return get_phys_addr_v5(env, ptw, address, access_type, result, fi); in get_phys_addr_nogpc()
3526 ARMMMUFaultInfo *fi) in get_phys_addr_gpc() argument
3529 memop, result, fi)) { in get_phys_addr_gpc()
3533 result->f.attrs.space, fi)) { in get_phys_addr_gpc()
3534 fi->type = ARMFault_GPCFOnOutput; in get_phys_addr_gpc()
3544 ARMMMUFaultInfo *fi) in get_phys_addr_with_space_nogpc() argument
3551 memop, result, fi); in get_phys_addr_with_space_nogpc()
3622 GetPhysAddrResult *result, ARMMMUFaultInfo *fi) in get_phys_addr() argument
3630 memop, result, fi); in get_phys_addr()
3642 ARMMMUFaultInfo fi = {}; in arm_cpu_get_phys_page() local
3643 bool ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, 0, &res, &fi); in arm_cpu_get_phys_page()