Lines Matching full:3
292 if (!is_a64(env) && arm_current_el(env) == 3 && in access_el3_aa32ns()
309 if (arm_current_el(env) == 3) { in access_trap_aa32s_el1()
335 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { in access_tpm()
455 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
477 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
585 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && in cpacr_write()
602 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && in cpacr_read()
628 } else if (arm_current_el(env) < 3 && in cpacr_access()
629 FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { in cpacr_access()
642 FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { in cptr_access()
676 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
895 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { in pmreg_access()
909 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 in pmreg_access_xevcntr()
939 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { in pmreg_access_selr()
1497 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_writefn()
1504 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_rawwrite()
1526 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_readfn()
1584 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_writefn()
1590 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_readfn()
1597 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_rawwrite()
1605 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_rawread()
1673 if (arm_el_is_aa64(env, 3)) { in scr_write()
1897 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
1910 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
1916 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
1924 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
1937 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
1949 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
1960 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
1974 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
1987 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
1998 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
2009 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
2022 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
2036 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
2043 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
2049 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
2061 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
2071 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
2077 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
2087 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
2094 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
2095 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
2119 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
2126 { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
2134 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
2185 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
2196 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
2201 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
2208 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
2259 case 3: in gt_cntfrq_access()
2406 case 3: in gt_stimer_access()
2441 case 3: in gt_sel2timer_access()
3150 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
3157 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
3182 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
3191 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
3200 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
3224 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
3229 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
3235 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
3247 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
3257 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
3280 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
3289 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
3298 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
3312 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
3320 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
3328 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
3348 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
3358 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 5,
3387 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 6,
3414 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
3420 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
3432 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
3537 target_el = 3; in do_ats_write()
3552 if (current_el == 3) { in do_ats_write()
3553 target_el = 3; in do_ats_write()
3678 case 3: in ats_write()
3702 case 3: in ats_write()
3776 if (arm_current_el(env) == 3 && in at_s1e2_access()
3854 mask = 3; in simple_mpu_ap_bits()
3869 mask = 3; in extended_mpu_ap_bits()
4071 (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); in pmsav8r_regn_write()
4100 (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); in pmsav8r_regn_read()
4125 .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 0,
4130 .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 1,
4140 .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 0,
4144 .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 1,
4199 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
4219 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
4221 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
4244 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when in vmsa_ttbcr_write()
4247 value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); in vmsa_ttbcr_write()
4341 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
4351 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
4357 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
4365 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
4373 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
4385 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
4394 .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3,
4398 offsetofhigh32(CPUARMState, cp15.tcr_el[3]),
4450 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
4555 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
4558 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
4613 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
4619 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
4690 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3,
4708 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4,
4726 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5,
4744 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6,
5005 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
5008 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
5014 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
5018 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
5022 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
5027 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
5036 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
5053 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
5075 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
5084 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
5089 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
5115 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
5146 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
5180 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
5187 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
5193 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
5203 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
5208 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
5213 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
5218 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
5223 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
5228 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
5233 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
5238 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
5244 .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
5253 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
5258 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
5263 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
5567 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 2,
5608 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && in cptr_el2_write()
5624 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && in cptr_el2_read()
5634 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
5645 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
5649 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
5654 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
5658 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
5667 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
5671 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
5676 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
5680 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
5685 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
5693 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
5698 .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
5702 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
5706 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
5710 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
5720 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
5732 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
5737 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
5741 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
5746 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
5782 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
5785 * reset values as IMPDEF. We choose to reset to 3 to comply with
5788 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 3,
5792 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
5802 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
5811 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
5817 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
5828 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
5832 .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
5850 if (arm_current_el(env) == 3 || arm_is_secure_below_el3(env)) { in sel2_access()
5858 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 0,
5863 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2,
5870 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 0,
5878 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 1,
5886 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 2,
5894 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 0,
5902 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 1,
5910 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 2,
5926 if (arm_current_el(env) == 3) { in nsacr_access()
5944 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
5953 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
5965 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
5967 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
5969 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
5973 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
5976 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
5978 .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
5980 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
5981 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
5983 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
5984 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
5987 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
5991 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
5993 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
5996 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
5998 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
6000 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
6002 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
6004 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
6008 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
6012 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
6145 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), in define_arm_vh_e2h_redirects_aliases()
6147 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), in define_arm_vh_e2h_redirects_aliases()
6149 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), in define_arm_vh_e2h_redirects_aliases()
6151 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), in define_arm_vh_e2h_redirects_aliases()
6153 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), in define_arm_vh_e2h_redirects_aliases()
6155 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), in define_arm_vh_e2h_redirects_aliases()
6157 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), in define_arm_vh_e2h_redirects_aliases()
6159 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), in define_arm_vh_e2h_redirects_aliases()
6161 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), in define_arm_vh_e2h_redirects_aliases()
6163 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), in define_arm_vh_e2h_redirects_aliases()
6165 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), in define_arm_vh_e2h_redirects_aliases()
6167 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), in define_arm_vh_e2h_redirects_aliases()
6169 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), in define_arm_vh_e2h_redirects_aliases()
6171 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), in define_arm_vh_e2h_redirects_aliases()
6173 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), in define_arm_vh_e2h_redirects_aliases()
6175 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), in define_arm_vh_e2h_redirects_aliases()
6183 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), in define_arm_vh_e2h_redirects_aliases()
6185 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6), in define_arm_vh_e2h_redirects_aliases()
6188 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), in define_arm_vh_e2h_redirects_aliases()
6191 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), in define_arm_vh_e2h_redirects_aliases()
6345 if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { in disr_read()
6359 if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { in disr_write()
6390 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
6394 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
6399 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
6403 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
6456 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, EZ)) { in sve_exception_el()
6457 return 3; in sve_exception_el()
6505 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { in sme_exception_el()
6506 return 3; in sme_exception_el()
6534 len = MIN(len, 0xf & (uint32_t)cr[3]); in sve_vqm1_for_el_sm()
6559 /* Bits other than [3:0] are RAZ/WI. */ in zcr_write()
6575 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
6581 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
6586 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
6588 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
6604 if (el < 3 in access_tpidr2()
6618 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { in access_smprimap()
6627 if (arm_current_el(env) < 3 in access_smpri()
6629 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { in access_smpri()
6706 .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5,
6711 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2,
6716 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 6,
6722 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 6,
6727 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 6,
6729 .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[3]),
6732 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 6,
6745 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4,
6750 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5,
6775 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6,
6779 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 4,
6782 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 5,
6818 .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 4, .crm = 3,
6846 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, in define_pmu_regs()
6865 .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, in define_pmu_regs()
6871 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), in define_pmu_regs()
6879 .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, in define_pmu_regs()
6885 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), in define_pmu_regs()
6916 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6, in define_pmu_regs()
6967 if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { in access_lor_ns()
6990 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
6995 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
7000 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
7005 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
7010 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
7026 if (el < 3 && in access_pauth()
7036 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0,
7041 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1,
7046 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2,
7051 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3,
7056 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0,
7061 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1,
7066 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0,
7071 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1,
7076 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2,
7081 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
7117 .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0,
7121 .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1,
7161 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
7169 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
7195 if (el < 3 && in access_mte()
7235 if (el < 3 && in access_tfsr_el2()
7255 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1,
7259 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0,
7265 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0,
7269 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0,
7271 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) },
7273 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5,
7277 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
7281 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
7285 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
7322 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
7328 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
7333 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
7338 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
7343 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
7348 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
7353 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
7358 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
7363 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
7368 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,
7377 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4,
7406 if (el < 3 in access_scxtnum()
7428 .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
7433 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
7439 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
7443 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
7445 .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
7460 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
7465 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 5,
7470 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 4,
7475 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 5,
7480 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 6,
7501 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 2, .opc2 = 0,
7529 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
7533 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
7537 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
7544 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
7548 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
7552 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
7565 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2,
7633 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
7640 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
7646 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2,
7652 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0,
7658 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1,
7663 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1,
7670 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1,
7677 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0,
7682 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0,
7687 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2,
7694 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2,
7740 .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3,
7744 .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
7777 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, in register_cp_regs_for_features()
7786 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, in register_cp_regs_for_features()
7800 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, in register_cp_regs_for_features()
7805 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, in register_cp_regs_for_features()
7810 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, in register_cp_regs_for_features()
7815 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, in register_cp_regs_for_features()
7820 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, in register_cp_regs_for_features()
7825 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, in register_cp_regs_for_features()
7830 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, in register_cp_regs_for_features()
7835 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, in register_cp_regs_for_features()
7840 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, in register_cp_regs_for_features()
7845 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, in register_cp_regs_for_features()
7850 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, in register_cp_regs_for_features()
7855 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, in register_cp_regs_for_features()
7860 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, in register_cp_regs_for_features()
7865 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, in register_cp_regs_for_features()
7884 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, in register_cp_regs_for_features()
7915 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, in register_cp_regs_for_features()
7928 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, in register_cp_regs_for_features()
7933 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, in register_cp_regs_for_features()
7938 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, in register_cp_regs_for_features()
7943 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, in register_cp_regs_for_features()
7948 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, in register_cp_regs_for_features()
7953 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, in register_cp_regs_for_features()
7958 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, in register_cp_regs_for_features()
7963 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, in register_cp_regs_for_features()
7968 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, in register_cp_regs_for_features()
7973 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, in register_cp_regs_for_features()
7978 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, in register_cp_regs_for_features()
7983 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, in register_cp_regs_for_features()
7988 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, in register_cp_regs_for_features()
7993 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, in register_cp_regs_for_features()
7998 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, in register_cp_regs_for_features()
8003 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, in register_cp_regs_for_features()
8008 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, in register_cp_regs_for_features()
8013 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, in register_cp_regs_for_features()
8018 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, in register_cp_regs_for_features()
8023 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, in register_cp_regs_for_features()
8028 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, in register_cp_regs_for_features()
8033 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, in register_cp_regs_for_features()
8038 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, in register_cp_regs_for_features()
8043 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, in register_cp_regs_for_features()
8048 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, in register_cp_regs_for_features()
8053 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, in register_cp_regs_for_features()
8058 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, in register_cp_regs_for_features()
8063 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, in register_cp_regs_for_features()
8068 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, in register_cp_regs_for_features()
8073 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, in register_cp_regs_for_features()
8078 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, in register_cp_regs_for_features()
8083 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, in register_cp_regs_for_features()
8088 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, in register_cp_regs_for_features()
8093 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, in register_cp_regs_for_features()
8104 .cp = 15, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, in register_cp_regs_for_features()
8109 .cp = 15, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, in register_cp_regs_for_features()
8114 .cp = 15, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, in register_cp_regs_for_features()
8125 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, in register_cp_regs_for_features()
8130 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, in register_cp_regs_for_features()
8135 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, in register_cp_regs_for_features()
8140 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, in register_cp_regs_for_features()
8145 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, in register_cp_regs_for_features()
8155 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, in register_cp_regs_for_features()
8165 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, in register_cp_regs_for_features()
8281 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, in register_cp_regs_for_features()
8285 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, in register_cp_regs_for_features()
8340 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, in register_cp_regs_for_features()
8352 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, in register_cp_regs_for_features()
8364 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, in register_cp_regs_for_features()
8385 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, in register_cp_regs_for_features()
8393 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 2, in register_cp_regs_for_features()
8405 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, in register_cp_regs_for_features()
8409 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 2, in register_cp_regs_for_features()
8416 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, in register_cp_regs_for_features()
8419 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), in register_cp_regs_for_features()
8571 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ in register_cp_regs_for_features()
8573 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, in register_cp_regs_for_features()
8590 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, in register_cp_regs_for_features()
8600 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, in register_cp_regs_for_features()
8618 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, in register_cp_regs_for_features()
8632 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, in register_cp_regs_for_features()
8709 uint8_t crm = 0b1000 | extract32(i, 1, 3); in register_cp_regs_for_features()
8739 uint8_t crm = 0b1000 | extract32(i, 1, 3); in register_cp_regs_for_features()
8774 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, in register_cp_regs_for_features()
8791 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, in register_cp_regs_for_features()
8796 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, in register_cp_regs_for_features()
8800 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, in register_cp_regs_for_features()
8831 .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, in register_cp_regs_for_features()
8835 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, in register_cp_regs_for_features()
8861 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, in register_cp_regs_for_features()
8877 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, in register_cp_regs_for_features()
8978 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, in register_cp_regs_for_features()
9322 case 3: in define_one_arm_cp_reg_with_opaque()
9553 return arm_current_el(env) < 3; in bad_mode_switch()
9564 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) in cpsr_read()
9565 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) in cpsr_read()
9581 env->VF = (val << 3) & 0x80000000; in cpsr_write()
9590 env->condexec_bits &= ~3; in cpsr_write()
9591 env->condexec_bits |= (val >> 25) & 3; in cpsr_write()
9594 env->condexec_bits &= 3; in cpsr_write()
9782 * 0-3 = EL0-EL3
9801 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9802 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
9803 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9804 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
9805 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9806 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
9807 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9808 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
9813 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9814 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
9815 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
9816 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
10186 case 3: in take_aarch32_exception()
10331 moe = 3; in arm_cpu_do_interrupt_aarch32()
10643 case 3: in arm_cpu_do_interrupt_aarch64()
10680 if (new_el == 3 && (env->cp15.scr_el3 & SCR_EASE) && in arm_cpu_do_interrupt_aarch64()
10766 * by setting M[3:2] to 0b10. in arm_cpu_do_interrupt_aarch64()
10950 el = 3; in arm_sctlr()
10968 return extract32(tcr, 20, 1) * 3; in aa64_va_parameter_tbi()
10980 return extract32(tcr, 29, 1) * 3; in aa64_va_parameter_tbid()
10990 return extract32(tcr, 30, 1) * 3; in aa64_va_parameter_tcma()
11015 case 3: in tg1_to_gran_size()
11101 ps = extract32(tcr, 16, 3); in aa64_va_parameters()
11128 ps = extract64(tcr, 32, 3); in aa64_va_parameters()
11246 return 3; in fp_exception_el()
11259 * 3 : trap no accesses in fp_exception_el()
11274 if (!arm_el_is_aa64(env, 3) in fp_exception_el()
11275 && (cur_el == 3 || arm_is_secure_below_el3(env))) { in fp_exception_el()
11276 return 3; in fp_exception_el()
11290 if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && in fp_exception_el()
11322 if (FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TFP)) { in fp_exception_el()
11324 return 3; in fp_exception_el()
11351 return 3; in arm_mmu_idx_to_el()
11380 !arm_el_is_aa64(env, 3)) { in arm_mmu_idx_el()
11405 case 3: in arm_mmu_idx_el()
11406 if (!arm_el_is_aa64(env, 3) && arm_pan_enabled(env)) { in arm_mmu_idx_el()
11451 if (vq & 3) { in aarch64_sve_narrow_vq()
11452 pmask = ~(-1ULL << (16 * (vq & 3))); in aarch64_sve_narrow_vq()
11554 if (extract32(env->pstate, 2, 2) == 3) { in arm_security_space()