Lines Matching +full:- +full:- +full:enable +full:- +full:safe +full:- +full:stack
6 * SPDX-License-Identifier: GPL-2.0-or-later
14 #include "cpu-features.h"
15 #include "exec/page-protection.h"
16 #include "exec/mmap-lock.h"
17 #include "qemu/main-loop.h"
20 #include "qemu/qemu-print.h"
22 #include "exec/translation-block.h"
24 #include "system/cpu-timers.h"
29 #include "qemu/guest-random.h"
33 #include "semihosting/common-semi.h"
39 #include "exec/helper-proto.h.inc"
47 assert(ri->fieldoffset); in raw_read()
57 assert(ri->fieldoffset); in raw_write()
67 return (char *)env + ri->fieldoffset; in raw_ptr()
73 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg()
74 return ri->resetvalue; in read_raw_cp_reg()
75 } else if (ri->raw_readfn) { in read_raw_cp_reg()
76 return ri->raw_readfn(env, ri); in read_raw_cp_reg()
77 } else if (ri->readfn) { in read_raw_cp_reg()
78 return ri->readfn(env, ri); in read_raw_cp_reg()
89 * Note that constant registers are treated as write-ignored; the in write_raw_cp_reg()
93 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg()
95 } else if (ri->raw_writefn) { in write_raw_cp_reg()
96 ri->raw_writefn(env, ri, v); in write_raw_cp_reg()
97 } else if (ri->writefn) { in write_raw_cp_reg()
98 ri->writefn(env, ri, v); in write_raw_cp_reg()
111 * read/write_raw_cp_reg() is safe, because we can't distinguish "has in raw_accessors_invalid()
112 * read/write access functions which are safe for raw use" from "has in raw_accessors_invalid()
118 if ((ri->type & ARM_CP_CONST) || in raw_accessors_invalid()
119 ri->fieldoffset || in raw_accessors_invalid()
120 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { in raw_accessors_invalid()
128 /* Write the coprocessor state from cpu->env to the (index,value) list. */ in write_cpustate_to_list()
132 for (i = 0; i < cpu->cpreg_array_len; i++) { in write_cpustate_to_list()
133 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); in write_cpustate_to_list()
137 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); in write_cpustate_to_list()
142 if (ri->type & ARM_CP_NO_RAW) { in write_cpustate_to_list()
146 newval = read_raw_cp_reg(&cpu->env, ri); in write_cpustate_to_list()
149 * Only sync if the previous list->cpustate sync succeeded. in write_cpustate_to_list()
154 uint64_t oldval = cpu->cpreg_values[i]; in write_cpustate_to_list()
160 write_raw_cp_reg(&cpu->env, ri, oldval); in write_cpustate_to_list()
161 if (read_raw_cp_reg(&cpu->env, ri) != oldval) { in write_cpustate_to_list()
165 write_raw_cp_reg(&cpu->env, ri, newval); in write_cpustate_to_list()
167 cpu->cpreg_values[i] = newval; in write_cpustate_to_list()
177 for (i = 0; i < cpu->cpreg_array_len; i++) { in write_list_to_cpustate()
178 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); in write_list_to_cpustate()
179 uint64_t v = cpu->cpreg_values[i]; in write_list_to_cpustate()
182 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); in write_list_to_cpustate()
187 if (ri->type & ARM_CP_NO_RAW) { in write_list_to_cpustate()
192 * (to catch read-only registers and partially read-only in write_list_to_cpustate()
195 write_raw_cp_reg(&cpu->env, ri, v); in write_list_to_cpustate()
196 if (read_raw_cp_reg(&cpu->env, ri) != v) { in write_list_to_cpustate()
207 const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); in add_cpreg_to_list()
209 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { in add_cpreg_to_list()
210 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); in add_cpreg_to_list()
212 cpu->cpreg_array_len++; in add_cpreg_to_list()
221 ri = g_hash_table_lookup(cpu->cp_regs, key); in count_cpreg()
223 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { in count_cpreg()
224 cpu->cpreg_array_len++; in count_cpreg()
237 return -1; in cpreg_key_compare()
251 keys = g_hash_table_get_keys(cpu->cp_regs); in init_cpreg_list()
254 cpu->cpreg_array_len = 0; in init_cpreg_list()
258 arraylen = cpu->cpreg_array_len; in init_cpreg_list()
259 cpu->cpreg_indexes = g_new(uint64_t, arraylen); in init_cpreg_list()
260 cpu->cpreg_values = g_new(uint64_t, arraylen); in init_cpreg_list()
261 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); in init_cpreg_list()
262 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); in init_cpreg_list()
263 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; in init_cpreg_list()
264 cpu->cpreg_array_len = 0; in init_cpreg_list()
268 assert(cpu->cpreg_array_len == arraylen); in init_cpreg_list()
279 return env->pstate & PSTATE_PAN; in arm_pan_enabled()
281 return env->uncached_cpsr & CPSR_PAN; in arm_pan_enabled()
300 * Some secure-only AArch32 registers trap to EL3 if used from
301 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
313 if (env->cp15.scr_el3 & SCR_EEL2) { in access_trap_aa32s_el1()
335 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { in access_tpm()
432 * Define the secure and non-secure FCSE identifier CP registers
435 * v8 EL1 version of the register so the non-secure instance stands alone.
448 * Define the secure and non-secure context identifier CP registers
451 * non-secure case, the 32-bit register will have reset and migration
452 * disabled during registration as it is handled by the 64-bit instance.
502 * Not all pre-v6 cores implemented this WFI, so this is slightly
503 * over-broad.
511 * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
532 * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
571 * registers (D0-D31). in cpacr_write()
574 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ in cpacr_write()
582 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 in cpacr_write()
586 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { in cpacr_write()
588 value = (value & ~mask) | (env->cp15.cpacr_el1 & mask); in cpacr_write()
591 env->cp15.cpacr_el1 = value; in cpacr_write()
597 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 in cpacr_read()
600 uint64_t value = env->cp15.cpacr_el1; in cpacr_read()
603 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { in cpacr_read()
625 FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TCPAC)) { in cpacr_access()
629 FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { in cpacr_access()
642 FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { in cptr_access()
655 * We need to break the TB after ISB to execute self-modifying code
718 return -1; in swinc_ns_per()
781 return -1; in zero_event_ns_per()
840 * Empty supported_event_map and cpu->pmceid[01] before adding supported in pmu_init()
846 cpu->pmceid0 = 0; in pmu_init()
847 cpu->pmceid1 = 0; in pmu_init()
851 assert(cnt->number <= MAX_EVENT_ID); in pmu_init()
853 assert(cnt->number <= 0x3f); in pmu_init()
855 if (cnt->supported(&cpu->env)) { in pmu_init()
856 supported_event_map[cnt->number] = i; in pmu_init()
857 uint64_t event_mask = 1ULL << (cnt->number & 0x1f); in pmu_init()
858 if (cnt->number & 0x20) { in pmu_init()
859 cpu->pmceid1 |= event_mask; in pmu_init()
861 cpu->pmceid0 |= event_mask; in pmu_init()
889 if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { in pmreg_access()
895 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { in pmreg_access()
909 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 in pmreg_access_xevcntr()
924 && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 in pmreg_access_swinc()
939 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { in pmreg_access_selr()
953 && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 in pmreg_access_ccntr()
985 * We might be called for M-profile cores where MDCR_EL2 doesn't in pmu_counter_enabled()
986 * exist and arm_mdcr_el2_eff() will assert, so this early-exit check in pmu_counter_enabled()
998 e = env->cp15.c9_pmcr & PMCRE; in pmu_counter_enabled()
1002 enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); in pmu_counter_enabled()
1009 prohibited = prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); in pmu_counter_enabled()
1018 prohibited = prohibited && env->cp15.c9_pmcr & PMCRDP; in pmu_counter_enabled()
1021 prohibited = prohibited || (env->cp15.mdcr_el3 & MDCR_SCCD); in pmu_counter_enabled()
1030 filter = env->cp15.pmccfiltr_el0; in pmu_counter_enabled()
1032 filter = env->cp15.c14_pmevtyper[counter]; in pmu_counter_enabled()
1070 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && in pmu_update_irq()
1071 (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); in pmu_update_irq()
1079 * controlled by PMCR.D, but if PMCR.LC is set to enable the long in pmccntr_clockdiv_enabled()
1080 * (64-bit) cycle counter PMCR.D has no effect. in pmccntr_clockdiv_enabled()
1082 return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) == PMCRD; in pmccntr_clockdiv_enabled()
1101 bool hlp = env->cp15.mdcr_el2 & MDCR_HLP; in pmevcntr_is_64_bit()
1102 int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; in pmevcntr_is_64_bit()
1108 return env->cp15.c9_pmcr & PMCRLP; in pmevcntr_is_64_bit()
1112 * Ensure c15_ccnt is the guest-visible count so that operations such as
1114 * etc. can be done logically. This is essentially a no-op if the counter is
1127 uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; in pmccntr_op_start()
1129 uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ in pmccntr_op_start()
1131 if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { in pmccntr_op_start()
1132 env->cp15.c9_pmovsr |= (1ULL << 31); in pmccntr_op_start()
1136 env->cp15.c15_ccnt = new_pmccntr; in pmccntr_op_start()
1138 env->cp15.c15_ccnt_delta = cycles; in pmccntr_op_start()
1143 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1151 uint64_t remaining_cycles = -env->cp15.c15_ccnt; in pmccntr_op_finish()
1152 if (!(env->cp15.c9_pmcr & PMCRLC)) { in pmccntr_op_finish()
1163 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); in pmccntr_op_finish()
1168 uint64_t prev_cycles = env->cp15.c15_ccnt_delta; in pmccntr_op_finish()
1172 env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; in pmccntr_op_finish()
1179 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; in pmevcntr_op_start()
1187 uint64_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; in pmevcntr_op_start()
1191 if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & overflow_mask) { in pmevcntr_op_start()
1192 env->cp15.c9_pmovsr |= (1 << counter); in pmevcntr_op_start()
1195 env->cp15.c14_pmevcntr[counter] = new_pmevcntr; in pmevcntr_op_start()
1197 env->cp15.c14_pmevcntr_delta[counter] = count; in pmevcntr_op_start()
1204 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; in pmevcntr_op_finish()
1206 uint64_t delta = -(env->cp15.c14_pmevcntr[counter] + 1); in pmevcntr_op_finish()
1220 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); in pmevcntr_op_finish()
1225 env->cp15.c14_pmevcntr_delta[counter] -= in pmevcntr_op_finish()
1226 env->cp15.c14_pmevcntr[counter]; in pmevcntr_op_finish()
1250 pmu_op_start(&cpu->env); in pmu_pre_el_change()
1255 pmu_op_finish(&cpu->env); in pmu_post_el_change()
1265 * has the effect of setting the cpu->pmu_timer to the next earliest time a in arm_pmu_timer_cb()
1268 pmu_op_start(&cpu->env); in arm_pmu_timer_cb()
1269 pmu_op_finish(&cpu->env); in arm_pmu_timer_cb()
1279 env->cp15.c15_ccnt = 0; in pmcr_write()
1285 env->cp15.c14_pmevcntr[i] = 0; in pmcr_write()
1289 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; in pmcr_write()
1290 env->cp15.c9_pmcr |= (value & PMCR_WRITABLE_MASK); in pmcr_write()
1297 uint64_t pmcr = env->cp15.c9_pmcr; in pmcr_read()
1305 pmcr |= (env->cp15.mdcr_el2 & MDCR_HPMN) << PMCRN_SHIFT; in pmcr_read()
1323 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { in pmswinc_write()
1330 new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; in pmswinc_write()
1335 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & overflow_mask) { in pmswinc_write()
1336 env->cp15.c9_pmovsr |= (1 << i); in pmswinc_write()
1340 env->cp15.c14_pmevcntr[i] = new_pmswinc; in pmswinc_write()
1351 ret = env->cp15.c15_ccnt; in pmccntr_read()
1365 env->cp15.c9_pmselr = value & 0x1f; in pmselr_write()
1372 env->cp15.c15_ccnt = value; in pmccntr_write()
1388 env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; in pmccfiltr_write()
1397 env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | in pmccfiltr_write_a32()
1405 return env->cp15.pmccfiltr_el0 & PMCCFILTR; in pmccfiltr_read_a32()
1413 env->cp15.c9_pmcnten |= value; in pmcntenset_write()
1422 env->cp15.c9_pmcnten &= ~value; in pmcntenclr_write()
1430 env->cp15.c9_pmovsr &= ~value; in pmovsr_write()
1438 env->cp15.c9_pmovsr |= value; in pmovsset_write()
1456 uint16_t old_event = env->cp15.c14_pmevtyper[counter] & in pmevtyper_write()
1465 env->cp15.c14_pmevcntr_delta[counter] = count; in pmevtyper_write()
1468 env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; in pmevtyper_write()
1482 return env->cp15.pmccfiltr_el0; in pmevtyper_read()
1484 return env->cp15.c14_pmevtyper[counter]; in pmevtyper_read()
1497 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_writefn()
1504 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_rawwrite()
1505 env->cp15.c14_pmevtyper[counter] = value; in pmevtyper_rawwrite()
1519 env->cp15.c14_pmevcntr_delta[counter] = in pmevtyper_rawwrite()
1526 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_readfn()
1533 pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); in pmxevtyper_write()
1538 return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); in pmxevtyper_read()
1550 env->cp15.c14_pmevcntr[counter] = value; in pmevcntr_write()
1565 ret = env->cp15.c14_pmevcntr[counter]; in pmevcntr_read()
1584 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_writefn()
1590 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_readfn()
1597 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_rawwrite()
1599 env->cp15.c14_pmevcntr[counter] = value; in pmevcntr_rawwrite()
1605 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_rawread()
1607 return env->cp15.c14_pmevcntr[counter]; in pmevcntr_rawread()
1613 pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); in pmxevcntr_write()
1618 return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); in pmxevcntr_read()
1625 env->cp15.c9_pmuserenr = value & 0xf; in pmuserenr_write()
1627 env->cp15.c9_pmuserenr = value & 1; in pmuserenr_write()
1636 env->cp15.c9_pminten |= value; in pmintenset_write()
1644 env->cp15.c9_pminten &= ~value; in pmintenclr_write()
1743 /* Clear all-context RES0 bits. */ in scr_write()
1745 changed = env->cp15.scr_el3 ^ value; in scr_write()
1746 env->cp15.scr_el3 = value; in scr_write()
1766 * scr_write will set the RES1 bits on an AArch64-only CPU. in scr_reset()
1767 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise. in scr_reset()
1793 ri->secure & ARM_CP_SECSTATE_S); in ccsidr_read()
1795 return cpu->ccsidr[index]; in ccsidr_read()
1812 if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { in isr_read()
1815 if (cs->interrupt_request & CPU_INTERRUPT_VINMI) { in isr_read()
1820 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { in isr_read()
1824 if (cs->interrupt_request & CPU_INTERRUPT_NMI) { in isr_read()
1831 if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { in isr_read()
1834 if (cs->interrupt_request & CPU_INTERRUPT_VFNMI) { in isr_read()
1839 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { in isr_read()
1845 if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { in isr_read()
2083 * MAIR can just read-as-written because we don't implement caches
2098 * For non-long-descriptor page tables these are PRRR and NMRR;
2099 * regardless they still act as reads-as-written for QEMU.
2102 * MAIR0/1 are defined separately from their 64-bit counterpart which
2147 env->teecr = value; in teecr_write()
2158 (env->cp15.hstr_el2 & HSTR_TTEE)) { in teecr_access()
2167 if (arm_current_el(env) == 0 && (env->teecr & 1)) { in teehbr_access()
2223 cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; in arm_gt_cntfrq_reset()
2243 cntkctl = env->cp15.cnthctl_el2; in gt_cntfrq_access()
2245 cntkctl = env->cp15.c14_cntkctl; in gt_cntfrq_access()
2252 if (!isread && ri->state == ARM_CP_STATE_AA32 && in gt_cntfrq_access()
2254 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ in gt_cntfrq_access()
2281 return (extract32(env->cp15.cnthctl_el2, timeridx, 1) in gt_counter_access()
2286 if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { in gt_counter_access()
2294 ? !extract32(env->cp15.cnthctl_el2, 10, 1) in gt_counter_access()
2295 : !extract32(env->cp15.cnthctl_el2, 0, 1))) { in gt_counter_access()
2299 if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVCT)) { in gt_counter_access()
2319 return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) in gt_timer_access()
2327 if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { in gt_timer_access()
2336 if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { in gt_timer_access()
2341 if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { in gt_timer_access()
2347 if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVT)) { in gt_timer_access()
2399 if (!(env->cp15.scr_el3 & SCR_ST)) { in gt_stimer_access()
2442 if (env->cp15.scr_el3 & SCR_EEL2) { in gt_sel2timer_access()
2461 CPUARMState *env = &cpu->env; in gt_update_irq()
2462 uint64_t cnthctl = env->cp15.cnthctl_el2; in gt_update_irq()
2465 int irqstate = (env->cp15.c14_timer[timeridx].ctl & 6) == 4; in gt_update_irq()
2477 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); in gt_update_irq()
2494 if ((env->cp15.scr_el3 & SCR_ECVEN) && in gt_phys_raw_cnt_offset()
2495 FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) && in gt_phys_raw_cnt_offset()
2498 return env->cp15.cntpoff_el2; in gt_phys_raw_cnt_offset()
2519 return env->cp15.cntvoff_el2; in gt_indirect_access_timer_offset()
2538 * This isn't exactly the same as the indirect-access offset, in gt_direct_access_timer_offset()
2567 return env->cp15.cntvoff_el2; in gt_direct_access_timer_offset()
2581 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; in gt_recalc_timer()
2583 if (gt->ctl & 1) { in gt_recalc_timer()
2588 uint64_t offset = gt_indirect_access_timer_offset(&cpu->env, timeridx); in gt_recalc_timer()
2589 uint64_t count = gt_get_countervalue(&cpu->env); in gt_recalc_timer()
2591 int istatus = count - offset >= gt->cval; in gt_recalc_timer()
2594 gt->ctl = deposit32(gt->ctl, 2, 1, istatus); in gt_recalc_timer()
2598 * Next transition is when (count - offset) rolls back over to 0. in gt_recalc_timer()
2611 * Next transition is when (count - offset) == cval, i.e. in gt_recalc_timer()
2616 if (uadd64_overflow(gt->cval, offset, &nexttick)) { in gt_recalc_timer()
2622 * signed-64-bit range of a QEMUTimer -- in this case we just in gt_recalc_timer()
2627 timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); in gt_recalc_timer()
2629 timer_mod(cpu->gt_timer[timeridx], nexttick); in gt_recalc_timer()
2634 gt->ctl &= ~4; in gt_recalc_timer()
2635 timer_del(cpu->gt_timer[timeridx]); in gt_recalc_timer()
2646 timer_del(cpu->gt_timer[timeridx]); in gt_timer_reset()
2652 return gt_get_countervalue(env) - offset; in gt_cnt_read()
2658 return gt_get_countervalue(env) - offset; in gt_virt_cnt_read()
2666 env->cp15.c14_timer[timeridx].cval = value; in gt_cval_write()
2672 return (uint32_t)(env->cp15.c14_timer[timeridx].cval - in do_tval_read()
2673 (gt_get_countervalue(env) - offset)); in do_tval_read()
2688 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + in do_tval_write()
2707 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; in gt_ctl_write()
2710 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); in gt_ctl_write()
2712 /* Enable toggled */ in gt_ctl_write()
2780 return env->cp15.c14_timer[timeridx].cval; in gt_phys_redir_cval_read()
2808 return env->cp15.c14_timer[timeridx].ctl; in gt_phys_redir_ctl_read()
2835 * to re-detect that it's this register. in gt_virt_tval_read()
2838 return do_tval_read(env, GTIMER_VIRT, env->cp15.cntvoff_el2); in gt_virt_tval_read()
2845 do_tval_write(env, GTIMER_VIRT, value, env->cp15.cntvoff_el2); in gt_virt_tval_write()
2858 uint32_t oldval = env->cp15.cnthctl_el2; in gt_cnthctl_write()
2911 return env->cp15.c14_timer[timeridx].cval; in gt_virt_redir_cval_read()
2939 return env->cp15.c14_timer[timeridx].ctl; in gt_virt_redir_ctl_read()
3140 * Note that CNTFRQ is purely reads-as-written for the benefit
3162 /* per-timer control */
3308 * Secure timer -- this is actually restricted to only EL3
3309 * and configurably Secure-EL1 via the accessfn.
3338 * are "self-synchronizing". For QEMU all sysregs are self-synchronizing,
3369 !(env->cp15.scr_el3 & SCR_ECVEN)) { in gt_cntpoff_access()
3396 * In user-mode most of the generic timer registers are inaccessible
3405 * Currently we have no support for QEMUTimer in linux-user so we in gt_virt_cnt_read()
3415 .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
3452 /* get_phys_addr() isn't present for user-mode-only targets */
3457 if (ri->opc2 & 4) { in ats_access()
3466 if (env->cp15.scr_el3 & SCR_EEL2) { in ats_access()
3481 * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC in par_el1_shareability()
3482 * memory -- see pseudocode PAREncodeShareability(). in par_el1_shareability()
3484 if (((res->cacheattrs.attrs & 0xf0) == 0) || in par_el1_shareability()
3485 res->cacheattrs.attrs == 0x44 || res->cacheattrs.attrs == 0x40) { in par_el1_shareability()
3488 return res->cacheattrs.shareability; in par_el1_shareability()
3536 (env->cp15.scr_el3 & SCR_EA)) { in do_ats_write()
3539 env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; in do_ats_write()
3541 env->cp15.hpfar_el2 |= HPFAR_NS; in do_ats_write()
3579 env->exception.vaddress = value; in do_ats_write()
3580 env->exception.fsr = fsr; in do_ats_write()
3591 * 32-bit or the 64-bit PAR format in do_ats_write()
3595 * * The Non-secure TTBCR.EAE bit is set to 1 in do_ats_write()
3608 format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); in do_ats_write()
3616 /* Create a 64-bit PAR */ in do_ats_write()
3641 * Convert it to a 32-bit PAR. in do_ats_write()
3668 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; in ats_write()
3674 switch (ri->opc2 & 6) { in ats_write()
3679 if (ri->crm == 9 && arm_pan_enabled(env)) { in ats_write()
3686 g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ in ats_write()
3689 if (ri->crm == 9 && arm_pan_enabled(env)) { in ats_write()
3706 g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ in ats_write()
3743 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; in ats1h_write()
3767 if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) == SCR_NSE) { in at_e012_access()
3777 !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { in at_s1e2_access()
3796 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; in ats_write64()
3803 switch (ri->opc2 & 6) { in ats_write64()
3805 switch (ri->opc1) { in ats_write64()
3807 if (ri->crm == 9 && arm_pan_enabled(env)) { in ats_write64()
3839 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx, ss); in ats_write64()
3880 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); in pmsav5_data_ap_write()
3885 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); in pmsav5_data_ap_read()
3891 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); in pmsav5_insn_ap_write()
3896 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); in pmsav5_insn_ap_read()
3907 u32p += env->pmsav7.rnr[M_REG_NS]; in pmsav7_read()
3921 u32p += env->pmsav7.rnr[M_REG_NS]; in pmsav7_write()
3922 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in pmsav7_write()
3930 uint32_t nrgs = cpu->pmsav7_dregion; in pmsav7_rgnr_write()
3947 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in prbar_write()
3948 env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; in prbar_write()
3953 return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; in prbar_read()
3961 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in prlar_write()
3962 env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; in prlar_write()
3967 return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; in prlar_read()
3979 if (value >= cpu->pmsav7_dregion) { in prselr_write()
3983 env->pmsav7.rnr[M_REG_NS] = value; in prselr_write()
3991 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in hprbar_write()
3992 env->pmsav8.hprbar[env->pmsav8.hprselr] = value; in hprbar_write()
3997 return env->pmsav8.hprbar[env->pmsav8.hprselr]; in hprbar_read()
4005 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in hprlar_write()
4006 env->pmsav8.hprlar[env->pmsav8.hprselr] = value; in hprlar_write()
4011 return env->pmsav8.hprlar[env->pmsav8.hprselr]; in hprlar_read()
4022 int rmax = MIN(cpu->pmsav8r_hdregion, 32); in hprenr_write()
4025 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in hprenr_write()
4030 env->pmsav8.hprlar[n] = deposit32( in hprenr_write()
4031 env->pmsav8.hprlar[n], 0, 1, bit); in hprenr_write()
4042 for (n = 0; n < MIN(cpu->pmsav8r_hdregion, 32); ++n) { in hprenr_read()
4043 if (env->pmsav8.hprlar[n] & 0x1) { in hprenr_read()
4059 if (value >= cpu->pmsav8r_hdregion) { in hprselr_write()
4063 env->pmsav8.hprselr = value; in hprselr_write()
4070 uint8_t index = (extract32(ri->opc0, 0, 1) << 4) | in pmsav8r_regn_write()
4071 (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); in pmsav8r_regn_write()
4073 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ in pmsav8r_regn_write()
4075 if (ri->opc1 & 4) { in pmsav8r_regn_write()
4076 if (index >= cpu->pmsav8r_hdregion) { in pmsav8r_regn_write()
4079 if (ri->opc2 & 0x1) { in pmsav8r_regn_write()
4080 env->pmsav8.hprlar[index] = value; in pmsav8r_regn_write()
4082 env->pmsav8.hprbar[index] = value; in pmsav8r_regn_write()
4085 if (index >= cpu->pmsav7_dregion) { in pmsav8r_regn_write()
4088 if (ri->opc2 & 0x1) { in pmsav8r_regn_write()
4089 env->pmsav8.rlar[M_REG_NS][index] = value; in pmsav8r_regn_write()
4091 env->pmsav8.rbar[M_REG_NS][index] = value; in pmsav8r_regn_write()
4099 uint8_t index = (extract32(ri->opc0, 0, 1) << 4) | in pmsav8r_regn_read()
4100 (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); in pmsav8r_regn_read()
4102 if (ri->opc1 & 4) { in pmsav8r_regn_read()
4103 if (index >= cpu->pmsav8r_hdregion) { in pmsav8r_regn_read()
4106 if (ri->opc2 & 0x1) { in pmsav8r_regn_read()
4107 return env->pmsav8.hprlar[index]; in pmsav8r_regn_read()
4109 return env->pmsav8.hprbar[index]; in pmsav8r_regn_read()
4112 if (index >= cpu->pmsav7_dregion) { in pmsav8r_regn_read()
4115 if (ri->opc2 & 0x1) { in pmsav8r_regn_read()
4116 return env->pmsav8.rlar[M_REG_NS][index]; in pmsav8r_regn_read()
4118 return env->pmsav8.rbar[M_REG_NS][index]; in pmsav8r_regn_read()
4161 * because the PMSAv7 is also used by M-profile CPUs, which do
4245 * using Long-descriptor translation table format in vmsa_ttbcr_write()
4252 * Short-descriptor translation table format. in vmsa_ttbcr_write()
4283 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ in vmsa_ttbr_write()
4406 env->cp15.c15_ticonfig = value & 0xe7; in omap_ticonfig_write()
4408 env->cp15.c0_cpuid = (value & (1 << 5)) ? in omap_ticonfig_write()
4415 env->cp15.c15_threadid = value & 0xffff; in omap_threadid_write()
4421 /* Wait-for-interrupt (deprecated) */ in omap_wfi_write()
4432 env->cp15.c15_i_max = 0x000; in omap_cachemaint_write()
4433 env->cp15.c15_i_min = 0xff0; in omap_cachemaint_write()
4479 env->cp15.c15_cpar = value & 0x3fff; in xscale_cpar_write()
4492 * XScale specific cache-lockdown: since we have no cache we NOP these
4512 * implementation of this implementation-defined space.
4552 * The cache test-and-clean instructions always return (1 << 30)
4576 return env->cp15.vpidr_el2; in midr_read()
4584 uint64_t mpidr = cpu->mp_affinity; in mpidr_read_val()
4589 * Cores which are uniprocessor (non-coherent) in mpidr_read_val()
4591 * bit 30. (For instance, Cortex-R5). in mpidr_read_val()
4593 if (cpu->mp_is_up) { in mpidr_read_val()
4605 return env->cp15.vmpidr_el2; in mpidr_read()
4674 env->daif = value & PSTATE_DAIF; in aa64_daif_write()
4679 return env->pstate & PSTATE_PAN; in aa64_pan_read()
4685 env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); in aa64_pan_write()
4697 return env->pstate & PSTATE_UAO; in aa64_uao_read()
4703 env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); in aa64_uao_write()
4715 return env->pstate & PSTATE_DIT; in aa64_dit_read()
4721 env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); in aa64_dit_write()
4733 return env->pstate & PSTATE_SSBS; in aa64_ssbs_read()
4739 env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); in aa64_ssbs_write()
4813 if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { in aa64_zva_access()
4817 if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { in aa64_zva_access()
4840 return cpu->dcz_blocksize | dzp_bit; in aa64_dczid_read()
4846 if (!(env->pstate & PSTATE_SP)) { in sp_el0_access()
4849 * the stack pointer. in sp_el0_access()
4858 return env->pstate & PSTATE_SP; in spsel_read()
4871 if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { in sctlr_write()
4878 if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) { in sctlr_write()
4879 if (ri->opc1 == 6) { /* SCTLR_EL3 */ in sctlr_write()
4897 /* This may enable/disable the MMU, so do a TLB flush. */ in sctlr_write()
4900 if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) { in sctlr_write()
4919 bool pmu_op = (env->cp15.mdcr_el3 ^ value) & MDCR_EL3_PMU_ENABLE_BITS; in mdcr_el3_write()
4924 env->cp15.mdcr_el3 = value; in mdcr_el3_write()
4945 bool pmu_op = (env->cp15.mdcr_el2 ^ value) & MDCR_EL2_PMU_ENABLE_BITS; in mdcr_el2_write()
4950 env->cp15.mdcr_el2 = value; in mdcr_el2_write()
4971 * `IC IVAU` is handled to improve compatibility with JITs that dual-map their
4987 icache_line_mask = (4 << extract32(cpu->ctr, 0, 4)) - 1; in ic_ivau_write()
5001 * Minimal set of EL0-visible registers. This will need to be expanded
5030 /* Avoid overhead of an access check that always passes in user-mode */
5199 * state field when SPSel indicates that it's being used as the stack
5280 } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { in do_hcr_write()
5342 * HCR_PTW forbids certain page-table setups in do_hcr_write()
5348 if ((env->cp15.hcr_el2 ^ value) & in do_hcr_write()
5352 env->cp15.hcr_el2 = value; in do_hcr_write()
5384 value = deposit64(env->cp15.hcr_el2, 32, 32, value); in hcr_writehigh()
5392 value = deposit64(env->cp15.hcr_el2, 0, 32, value); in hcr_writelow()
5398 /* hcr_write will set the RES1 bits on an AArch64-only CPU */ in hcr_reset()
5409 uint64_t ret = env->cp15.hcr_el2; in arm_hcr_el2_eff_secstate()
5416 * current Security state". This is ARMv8.4-SecEL2 speak for in arm_hcr_el2_eff_secstate()
5423 * on a per-field basis. In current QEMU, this is condition in arm_hcr_el2_eff_secstate()
5441 * These bits are up-to-date as of ARMv8.6. in arm_hcr_el2_eff_secstate()
5452 /* These bits are up-to-date as of ARMv8.6. */ in arm_hcr_el2_eff_secstate()
5500 if ((env->cp15.hcr_el2 & mask) != mask) { in el_is_in_host()
5533 env->cp15.hcrx_el2 = value & valid_mask; in hcrx_write()
5558 && !(env->cp15.scr_el3 & SCR_HXEN)) { in access_hxen()
5581 * For the moment, we treat the EL2-disabled case as taking in arm_hcrx_el2_eff()
5582 * priority over the HXEn-disabled case. This is true for the only in arm_hcrx_el2_eff()
5595 if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXEN)) { in arm_hcrx_el2_eff()
5598 return env->cp15.hcrx_el2; in arm_hcrx_el2_eff()
5605 * For A-profile AArch32 EL3, if NSACR.CP10 in cptr_el2_write()
5609 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { in cptr_el2_write()
5611 value = (value & ~mask) | (env->cp15.cptr_el[2] & mask); in cptr_el2_write()
5613 env->cp15.cptr_el[2] = value; in cptr_el2_write()
5619 * For A-profile AArch32 EL3, if NSACR.CP10 in cptr_el2_read()
5622 uint64_t value = env->cp15.cptr_el[2]; in cptr_el2_read()
5625 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { in cptr_el2_read()
5755 * Unlike the other EL2-related AT operations, these must
5930 if (env->cp15.scr_el3 & SCR_EEL2) { in nsacr_access()
6037 if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVPCT)) { in access_el1nvpct()
6049 if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVVCT)) { in access_el1nvvct()
6068 ri = ri->opaque; in el2_e2h_read()
6069 readfn = ri->readfn; in el2_e2h_read()
6071 readfn = ri->orig_readfn; in el2_e2h_read()
6086 ri = ri->opaque; in el2_e2h_write()
6087 writefn = ri->writefn; in el2_e2h_write()
6089 writefn = ri->orig_writefn; in el2_e2h_write()
6100 return ri->orig_readfn(env, ri->opaque); in el2_e2h_e12_read()
6107 return ri->orig_writefn(env, ri->opaque, value); in el2_e2h_e12_write()
6127 if (ri->orig_accessfn) { in el2_e2h_e12_access()
6128 return ri->orig_accessfn(env, ri->opaque, isread); in el2_e2h_e12_access()
6195 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ in define_arm_vh_e2h_redirects_aliases()
6196 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ in define_arm_vh_e2h_redirects_aliases()
6207 if (a->feature && !a->feature(&cpu->isar)) { in define_arm_vh_e2h_redirects_aliases()
6211 src_reg = g_hash_table_lookup(cpu->cp_regs, in define_arm_vh_e2h_redirects_aliases()
6212 (gpointer)(uintptr_t)a->src_key); in define_arm_vh_e2h_redirects_aliases()
6213 dst_reg = g_hash_table_lookup(cpu->cp_regs, in define_arm_vh_e2h_redirects_aliases()
6214 (gpointer)(uintptr_t)a->dst_key); in define_arm_vh_e2h_redirects_aliases()
6218 /* Cross-compare names to detect typos in the keys. */ in define_arm_vh_e2h_redirects_aliases()
6219 g_assert(strcmp(src_reg->name, a->src_name) == 0); in define_arm_vh_e2h_redirects_aliases()
6220 g_assert(strcmp(dst_reg->name, a->dst_name) == 0); in define_arm_vh_e2h_redirects_aliases()
6223 g_assert(src_reg->opaque == NULL); in define_arm_vh_e2h_redirects_aliases()
6228 new_reg->name = a->new_name; in define_arm_vh_e2h_redirects_aliases()
6229 new_reg->type |= ARM_CP_ALIAS; in define_arm_vh_e2h_redirects_aliases()
6231 new_reg->access &= PL2_RW | PL3_RW; in define_arm_vh_e2h_redirects_aliases()
6233 new_reg->crn = (a->new_key & CP_REG_ARM64_SYSREG_CRN_MASK) in define_arm_vh_e2h_redirects_aliases()
6235 new_reg->crm = (a->new_key & CP_REG_ARM64_SYSREG_CRM_MASK) in define_arm_vh_e2h_redirects_aliases()
6237 new_reg->opc0 = (a->new_key & CP_REG_ARM64_SYSREG_OP0_MASK) in define_arm_vh_e2h_redirects_aliases()
6239 new_reg->opc1 = (a->new_key & CP_REG_ARM64_SYSREG_OP1_MASK) in define_arm_vh_e2h_redirects_aliases()
6241 new_reg->opc2 = (a->new_key & CP_REG_ARM64_SYSREG_OP2_MASK) in define_arm_vh_e2h_redirects_aliases()
6243 new_reg->opaque = src_reg; in define_arm_vh_e2h_redirects_aliases()
6244 new_reg->orig_readfn = src_reg->readfn ?: raw_read; in define_arm_vh_e2h_redirects_aliases()
6245 new_reg->orig_writefn = src_reg->writefn ?: raw_write; in define_arm_vh_e2h_redirects_aliases()
6246 new_reg->orig_accessfn = src_reg->accessfn; in define_arm_vh_e2h_redirects_aliases()
6247 if (!new_reg->raw_readfn) { in define_arm_vh_e2h_redirects_aliases()
6248 new_reg->raw_readfn = raw_read; in define_arm_vh_e2h_redirects_aliases()
6250 if (!new_reg->raw_writefn) { in define_arm_vh_e2h_redirects_aliases()
6251 new_reg->raw_writefn = raw_write; in define_arm_vh_e2h_redirects_aliases()
6253 new_reg->readfn = el2_e2h_e12_read; in define_arm_vh_e2h_redirects_aliases()
6254 new_reg->writefn = el2_e2h_e12_write; in define_arm_vh_e2h_redirects_aliases()
6255 new_reg->accessfn = el2_e2h_e12_access; in define_arm_vh_e2h_redirects_aliases()
6262 if (new_reg->nv2_redirect_offset) { in define_arm_vh_e2h_redirects_aliases()
6263 assert(new_reg->nv2_redirect_offset & NV2_REDIR_NV1); in define_arm_vh_e2h_redirects_aliases()
6264 new_reg->nv2_redirect_offset &= ~NV2_REDIR_NV1; in define_arm_vh_e2h_redirects_aliases()
6265 new_reg->nv2_redirect_offset |= NV2_REDIR_NO_NV1; in define_arm_vh_e2h_redirects_aliases()
6268 ok = g_hash_table_insert(cpu->cp_regs, in define_arm_vh_e2h_redirects_aliases()
6269 (gpointer)(uintptr_t)a->new_key, new_reg); in define_arm_vh_e2h_redirects_aliases()
6272 src_reg->opaque = dst_reg; in define_arm_vh_e2h_redirects_aliases()
6273 src_reg->orig_readfn = src_reg->readfn ?: raw_read; in define_arm_vh_e2h_redirects_aliases()
6274 src_reg->orig_writefn = src_reg->writefn ?: raw_write; in define_arm_vh_e2h_redirects_aliases()
6275 if (!src_reg->raw_readfn) { in define_arm_vh_e2h_redirects_aliases()
6276 src_reg->raw_readfn = raw_read; in define_arm_vh_e2h_redirects_aliases()
6278 if (!src_reg->raw_writefn) { in define_arm_vh_e2h_redirects_aliases()
6279 src_reg->raw_writefn = raw_write; in define_arm_vh_e2h_redirects_aliases()
6281 src_reg->readfn = el2_e2h_read; in define_arm_vh_e2h_redirects_aliases()
6282 src_reg->writefn = el2_e2h_write; in define_arm_vh_e2h_redirects_aliases()
6297 if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { in ctr_el0_access()
6301 if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { in ctr_el0_access()
6332 if (!arm_is_el3_or_mon(env) && (env->cp15.scr_el3 & SCR_TERR)) { in access_terr()
6343 return env->cp15.vdisr_el2; in disr_read()
6345 if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { in disr_read()
6348 return env->cp15.disr_el1; in disr_read()
6356 env->cp15.vdisr_el2 = val; in disr_write()
6359 if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { in disr_write()
6362 env->cp15.disr_el1 = val; in disr_write()
6384 * These registers have fine-grained trap bits, but UNDEF-to-EL1
6385 * is higher priority than FGT-to-EL2 so we do not need to list them
6422 switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { in sve_exception_el()
6436 if (env->cp15.hcr_el2 & HCR_E2H) { in sve_exception_el()
6437 switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { in sve_exception_el()
6439 if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { in sve_exception_el()
6448 if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { in sve_exception_el()
6456 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, EZ)) { in sve_exception_el()
6471 switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, SMEN)) { in sme_exception_el()
6485 if (env->cp15.hcr_el2 & HCR_E2H) { in sme_exception_el()
6486 switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, SMEN)) { in sme_exception_el()
6488 if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { in sme_exception_el()
6497 if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TSM)) { in sme_exception_el()
6505 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { in sme_exception_el()
6518 uint64_t *cr = env->vfp.zcr_el; in sve_vqm1_for_el_sm()
6519 uint32_t map = cpu->sve_vq.map; in sve_vqm1_for_el_sm()
6520 uint32_t len = ARM_MAX_VQ - 1; in sve_vqm1_for_el_sm()
6523 cr = env->vfp.smcr_el; in sve_vqm1_for_el_sm()
6524 map = cpu->sme_vq.map; in sve_vqm1_for_el_sm()
6539 return 31 - clz32(map); in sve_vqm1_for_el_sm()
6542 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */ in sve_vqm1_for_el_sm()
6544 return ctz32(cpu->sme_vq.map); in sve_vqm1_for_el_sm()
6549 return sve_vqm1_for_el_sm(env, el, FIELD_EX64(env->svcr, SVCR, SM)); in sve_vqm1_for_el()
6606 && !(env->cp15.scr_el3 & SCR_ENTP2)) { in access_tpidr2()
6618 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { in access_smprimap()
6629 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { in access_smpri()
6638 memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs)); in arm_reset_sve_state()
6640 memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs)); in arm_reset_sve_state()
6646 uint64_t change = (env->svcr ^ new) & mask; in aarch64_set_svcr()
6651 env->svcr ^= change; in aarch64_set_svcr()
6660 * SetPSTATE_ZA zeros on enable and disable. We can zero this only in aarch64_set_svcr()
6661 * on enable: while disabled, the storage is inaccessible and the in aarch64_set_svcr()
6666 memset(env->zarray, 0, sizeof(env->zarray)); in aarch64_set_svcr()
6677 aarch64_set_svcr(env, value, -1); in svcr_write()
6695 * apply the narrower SVL to the Zregs and Pregs -- see the comment in smcr_write()
6764 env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask); in gpccr_write()
6769 env->cp15.gpccr_el3 = FIELD_DP64(0, GPCCR, L0GPTSZ, in gpccr_reset()
6770 env_archcpu(env)->reset_l0gptsz); in gpccr_reset()
6798 env->pstate = (env->pstate & ~PSTATE_ALLINT) | (value & PSTATE_ALLINT); in aa64_allint_write()
6803 return env->pstate & PSTATE_ALLINT; in aa64_allint_read()
6833 unsigned int i, pmcrn = pmu_num_counters(&cpu->env); in define_pmu_regs()
6851 .resetvalue = cpu->isar.reset_pmcr_el0, in define_pmu_regs()
6904 .resetvalue = extract64(cpu->pmceid0, 32, 32) }, in define_pmu_regs()
6909 .resetvalue = extract64(cpu->pmceid1, 32, 32) }, in define_pmu_regs()
6935 uint64_t pfr1 = cpu->isar.id_pfr1; in id_pfr1_read()
6937 if (env->gicv3state) { in id_pfr1_read()
6946 uint64_t pfr0 = cpu->isar.id_aa64pfr0; in id_aa64pfr0_read()
6948 if (env->gicv3state) { in id_aa64pfr0_read()
6967 if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { in access_lor_ns()
6984 * A trivial implementation of ARMv8.1-LOR leaves all of these
7028 !(env->cp15.scr_el3 & SCR_APK)) { in access_pauth()
7093 env->NF = env->CF = env->VF = 0, env->ZF = 1; in rndr_readfn()
7099 * timed-out indication to the guest. There is no reason in rndr_readfn()
7104 ri->name, error_get_pretty(err)); in rndr_readfn()
7107 env->ZF = 0; /* NZCF = 0100 */ in rndr_readfn()
7113 /* We do not support re-seeding, so the two registers operate the same. */
7130 /* CTR_EL0 System register -> DminLine, bits [19:16] */ in dccvap_writefn()
7131 uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); in dccvap_writefn()
7133 uint64_t vaddr = vaddr_in & ~(dline_size - 1); in dccvap_writefn()
7197 !(env->cp15.scr_el3 & SCR_ATA)) { in access_mte()
7237 !(env->cp15.scr_el3 & SCR_ATA)) { in access_tfsr_el2()
7245 return env->pstate & PSTATE_TCO; in tco_read()
7250 env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); in tco_write()
7371 /* Avoid overhead of an access check that always passes in user-mode */
7380 /* Avoid overhead of an access check that always passes in user-mode */
7394 if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { in access_scxtnum()
7400 } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { in access_scxtnum()
7408 && !(env->cp15.scr_el3 & SCR_ENSCXT)) { in access_scxtnum()
7452 arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGTEN)) { in access_fgt()
7491 * that VNCR_EL2 + offset is 64-bit aligned. We don't need to do anything in vncr_write()
7492 * about the RESS bits at the top -- we choose the "generate an EL2 in vncr_write()
7496 env->cp15.vncr_el2 = value & ~0xfffULL; in vncr_write()
7610 (env->cp15.hstr_el2 & HSTR_TJDBX)) { in access_joscr_jmcr()
7732 * is non-zero, which is never for ARMv7, optionally in ARMv8
7752 CPUARMState *env = &cpu->env; in register_cp_regs_for_features()
7778 .resetvalue = cpu->isar.id_pfr0 }, in register_cp_regs_for_features()
7789 .resetvalue = cpu->isar.id_pfr1, in register_cp_regs_for_features()
7801 .resetvalue = cpu->isar.id_dfr0 }, in register_cp_regs_for_features()
7806 .resetvalue = cpu->id_afr0 }, in register_cp_regs_for_features()
7811 .resetvalue = cpu->isar.id_mmfr0 }, in register_cp_regs_for_features()
7816 .resetvalue = cpu->isar.id_mmfr1 }, in register_cp_regs_for_features()
7821 .resetvalue = cpu->isar.id_mmfr2 }, in register_cp_regs_for_features()
7826 .resetvalue = cpu->isar.id_mmfr3 }, in register_cp_regs_for_features()
7831 .resetvalue = cpu->isar.id_isar0 }, in register_cp_regs_for_features()
7836 .resetvalue = cpu->isar.id_isar1 }, in register_cp_regs_for_features()
7841 .resetvalue = cpu->isar.id_isar2 }, in register_cp_regs_for_features()
7846 .resetvalue = cpu->isar.id_isar3 }, in register_cp_regs_for_features()
7851 .resetvalue = cpu->isar.id_isar4 }, in register_cp_regs_for_features()
7856 .resetvalue = cpu->isar.id_isar5 }, in register_cp_regs_for_features()
7861 .resetvalue = cpu->isar.id_mmfr4 }, in register_cp_regs_for_features()
7866 .resetvalue = cpu->isar.id_isar6 }, in register_cp_regs_for_features()
7886 .resetvalue = cpu->clidr in register_cp_regs_for_features()
7917 .resetvalue = cpu->isar.id_aa64pfr0 in register_cp_regs_for_features()
7929 .resetvalue = cpu->isar.id_aa64pfr1}, in register_cp_regs_for_features()
7944 .resetvalue = cpu->isar.id_aa64zfr0 }, in register_cp_regs_for_features()
7949 .resetvalue = cpu->isar.id_aa64smfr0 }, in register_cp_regs_for_features()
7964 .resetvalue = cpu->isar.id_aa64dfr0 }, in register_cp_regs_for_features()
7969 .resetvalue = cpu->isar.id_aa64dfr1 }, in register_cp_regs_for_features()
7984 .resetvalue = cpu->id_aa64afr0 }, in register_cp_regs_for_features()
7989 .resetvalue = cpu->id_aa64afr1 }, in register_cp_regs_for_features()
8004 .resetvalue = cpu->isar.id_aa64isar0 }, in register_cp_regs_for_features()
8009 .resetvalue = cpu->isar.id_aa64isar1 }, in register_cp_regs_for_features()
8014 .resetvalue = cpu->isar.id_aa64isar2 }, in register_cp_regs_for_features()
8044 .resetvalue = cpu->isar.id_aa64mmfr0 }, in register_cp_regs_for_features()
8049 .resetvalue = cpu->isar.id_aa64mmfr1 }, in register_cp_regs_for_features()
8054 .resetvalue = cpu->isar.id_aa64mmfr2 }, in register_cp_regs_for_features()
8059 .resetvalue = cpu->isar.id_aa64mmfr3 }, in register_cp_regs_for_features()
8084 .resetvalue = cpu->isar.mvfr0 }, in register_cp_regs_for_features()
8089 .resetvalue = cpu->isar.mvfr1 }, in register_cp_regs_for_features()
8094 .resetvalue = cpu->isar.mvfr2 }, in register_cp_regs_for_features()
8119 * being filled with AArch64-view-of-AArch32-ID-register in register_cp_regs_for_features()
8131 .resetvalue = cpu->isar.id_pfr2 }, in register_cp_regs_for_features()
8136 .resetvalue = cpu->isar.id_dfr1 }, in register_cp_regs_for_features()
8141 .resetvalue = cpu->isar.id_mmfr5 }, in register_cp_regs_for_features()
8151 .resetvalue = extract64(cpu->pmceid0, 0, 32) }, in register_cp_regs_for_features()
8156 .resetvalue = cpu->pmceid0 }, in register_cp_regs_for_features()
8161 .resetvalue = extract64(cpu->pmceid1, 0, 32) }, in register_cp_regs_for_features()
8166 .resetvalue = cpu->pmceid1 }, in register_cp_regs_for_features()
8297 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32. in register_cp_regs_for_features()
8298 * For pre-v8 cores there are RAZ patterns for these in in register_cp_regs_for_features()
8301 * to also cover c0, 0, c{8-15}, {0-7}. in register_cp_regs_for_features()
8303 * c4-c7 is where the AArch64 ID registers live (and we've in register_cp_regs_for_features()
8304 * already defined those in v8_idregs[]), and c8-c15 are not in register_cp_regs_for_features()
8334 .resetvalue = cpu->midr, in register_cp_regs_for_features()
8339 .access = PL2_RW, .resetvalue = cpu->midr, in register_cp_regs_for_features()
8418 .resetvalue = cpu->reset_sctlr }, in register_cp_regs_for_features()
8475 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ in register_cp_regs_for_features()
8502 /* This underdecoding is safe because the reginfo is NO_RAW. */ in register_cp_regs_for_features()
8510 * When LPAE exists this 32-bit PAR register is an alias of the in register_cp_regs_for_features()
8511 * 64-bit AArch32 PAR register defined in lpae_cp_reginfo[] in register_cp_regs_for_features()
8547 * cp15 crn=0 to be writes-ignored, whereas for other cores they should in register_cp_regs_for_features()
8548 * be read-only (ie write causes UNDEF exception). in register_cp_regs_for_features()
8553 * Pre-v8 MIDR space. in register_cp_regs_for_features()
8564 .access = PL1_R, .resetvalue = cpu->midr, in register_cp_regs_for_features()
8589 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, in register_cp_regs_for_features()
8596 .access = PL1_R, .resetvalue = cpu->midr }, in register_cp_regs_for_features()
8602 .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, in register_cp_regs_for_features()
8607 .access = PL1_R, .resetvalue = cpu->midr in register_cp_regs_for_features()
8610 /* These are common to v8 and pre-v8 */ in register_cp_regs_for_features()
8614 .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, in register_cp_regs_for_features()
8619 .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, in register_cp_regs_for_features()
8620 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ in register_cp_regs_for_features()
8640 .resetvalue = cpu->pmsav7_dregion << 8 in register_cp_regs_for_features()
8647 .resetvalue = cpu->pmsav8r_hdregion in register_cp_regs_for_features()
8706 for (i = 0; i < MIN(cpu->pmsav7_dregion, 32); ++i) { in register_cp_regs_for_features()
8736 for (i = 0; i < MIN(cpu->pmsav8r_hdregion, 32); ++i) { in register_cp_regs_for_features()
8792 .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr }, in register_cp_regs_for_features()
8810 * CBAR is IMPDEF, but common on Arm Cortex-A implementations. in register_cp_regs_for_features()
8812 * (1) older 32-bit only cores have a simple 32-bit CBAR in register_cp_regs_for_features()
8813 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a in register_cp_regs_for_features()
8814 * 32-bit register visible to AArch32 at a different encoding in register_cp_regs_for_features()
8816 * be able to squash a 64-bit address into the 32-bit view. in register_cp_regs_for_features()
8818 * in future if we support AArch32-only configs of some of the in register_cp_regs_for_features()
8824 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) in register_cp_regs_for_features()
8825 | extract64(cpu->reset_cbar, 32, 12); in register_cp_regs_for_features()
8834 .access = PL1_R, .resetvalue = cpu->reset_cbar }, in register_cp_regs_for_features()
8843 .access = PL1_R | PL3_W, .resetvalue = cpu->reset_cbar, in register_cp_regs_for_features()
8881 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, in register_cp_regs_for_features()
8887 * arch/arm/mach-pxa/sleep.S expects two instructions following in register_cp_regs_for_features()
8888 * an MMU enable to execute from cache. Imitate this behaviour. in register_cp_regs_for_features()
8978 .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize, in register_cp_regs_for_features()
9040 CPUARMState *env = &cpu->env; in add_cpreg_to_hashtable()
9043 bool is64 = r->type & ARM_CP_64BIT; in add_cpreg_to_hashtable()
9045 int cp = r->cp; in add_cpreg_to_hashtable()
9052 if (cp == 0 && r->state == ARM_CP_STATE_BOTH) { in add_cpreg_to_hashtable()
9055 key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); in add_cpreg_to_hashtable()
9060 * cp == 0 as equivalent to the value for "standard guest-visible in add_cpreg_to_hashtable()
9062 * in their AArch64 view (the .cp value may be non-zero for the in add_cpreg_to_hashtable()
9065 if (cp == 0 || r->state == ARM_CP_STATE_BOTH) { in add_cpreg_to_hashtable()
9068 key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); in add_cpreg_to_hashtable()
9075 if (!(r->type & ARM_CP_OVERRIDE)) { in add_cpreg_to_hashtable()
9076 const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key); in add_cpreg_to_hashtable()
9078 assert(oldreg->type & ARM_CP_OVERRIDE); in add_cpreg_to_hashtable()
9093 int min_el = ctz32(r->access) / 2; in add_cpreg_to_hashtable()
9095 if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { in add_cpreg_to_hashtable()
9098 make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP); in add_cpreg_to_hashtable()
9103 if ((r->access & max_el) == 0) { in add_cpreg_to_hashtable()
9112 r2->name = memcpy(r2 + 1, name, name_len); in add_cpreg_to_hashtable()
9118 r2->cp = cp; in add_cpreg_to_hashtable()
9119 r2->crm = crm; in add_cpreg_to_hashtable()
9120 r2->opc1 = opc1; in add_cpreg_to_hashtable()
9121 r2->opc2 = opc2; in add_cpreg_to_hashtable()
9122 r2->state = state; in add_cpreg_to_hashtable()
9123 r2->secure = secstate; in add_cpreg_to_hashtable()
9125 r2->opaque = opaque; in add_cpreg_to_hashtable()
9130 int old_special = r2->type & ARM_CP_SPECIAL_MASK; in add_cpreg_to_hashtable()
9137 r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; in add_cpreg_to_hashtable()
9140 * special cases like VPIDR_EL2 which have a constant non-zero in add_cpreg_to_hashtable()
9143 if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { in add_cpreg_to_hashtable()
9144 r2->resetvalue = 0; in add_cpreg_to_hashtable()
9151 r2->readfn = NULL; in add_cpreg_to_hashtable()
9152 r2->writefn = NULL; in add_cpreg_to_hashtable()
9153 r2->raw_readfn = NULL; in add_cpreg_to_hashtable()
9154 r2->raw_writefn = NULL; in add_cpreg_to_hashtable()
9155 r2->resetfn = NULL; in add_cpreg_to_hashtable()
9156 r2->fieldoffset = 0; in add_cpreg_to_hashtable()
9157 r2->bank_fieldoffsets[0] = 0; in add_cpreg_to_hashtable()
9158 r2->bank_fieldoffsets[1] = 0; in add_cpreg_to_hashtable()
9160 bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; in add_cpreg_to_hashtable()
9168 r2->fieldoffset = r->bank_fieldoffsets[ns]; in add_cpreg_to_hashtable()
9174 * reset the 32-bit instance in certain cases: in add_cpreg_to_hashtable()
9176 * 1) If the register has both 32-bit and 64-bit instances in add_cpreg_to_hashtable()
9177 * then we can count on the 64-bit instance taking care in add_cpreg_to_hashtable()
9178 * of the non-secure bank. in add_cpreg_to_hashtable()
9179 * 2) If ARMv8 is enabled then we can count on a 64-bit in add_cpreg_to_hashtable()
9181 * that separate 32 and 64-bit definitions are provided. in add_cpreg_to_hashtable()
9183 if ((r->state == ARM_CP_STATE_BOTH && ns) || in add_cpreg_to_hashtable()
9185 r2->type |= ARM_CP_ALIAS; in add_cpreg_to_hashtable()
9187 } else if ((secstate != r->secure) && !ns) { in add_cpreg_to_hashtable()
9190 * migration of the non-secure instance. in add_cpreg_to_hashtable()
9192 r2->type |= ARM_CP_ALIAS; in add_cpreg_to_hashtable()
9196 r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { in add_cpreg_to_hashtable()
9197 r2->fieldoffset += sizeof(uint32_t); in add_cpreg_to_hashtable()
9207 * never migratable and not even raw-accessible. in add_cpreg_to_hashtable()
9209 if (r2->type & ARM_CP_SPECIAL_MASK) { in add_cpreg_to_hashtable()
9210 r2->type |= ARM_CP_NO_RAW; in add_cpreg_to_hashtable()
9212 if (((r->crm == CP_ANY) && crm != 0) || in add_cpreg_to_hashtable()
9213 ((r->opc1 == CP_ANY) && opc1 != 0) || in add_cpreg_to_hashtable()
9214 ((r->opc2 == CP_ANY) && opc2 != 0)) { in add_cpreg_to_hashtable()
9215 r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; in add_cpreg_to_hashtable()
9223 if (!(r2->type & ARM_CP_NO_RAW)) { in add_cpreg_to_hashtable()
9227 g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); in add_cpreg_to_hashtable()
9244 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard in define_one_arm_cp_reg_with_opaque()
9253 * Only registers visible in AArch64 may set r->opc0; opc0 cannot in define_one_arm_cp_reg_with_opaque()
9259 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; in define_one_arm_cp_reg_with_opaque()
9260 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; in define_one_arm_cp_reg_with_opaque()
9261 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; in define_one_arm_cp_reg_with_opaque()
9262 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; in define_one_arm_cp_reg_with_opaque()
9263 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; in define_one_arm_cp_reg_with_opaque()
9264 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; in define_one_arm_cp_reg_with_opaque()
9268 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); in define_one_arm_cp_reg_with_opaque()
9270 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); in define_one_arm_cp_reg_with_opaque()
9272 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); in define_one_arm_cp_reg_with_opaque()
9275 * (M-profile or v7A-and-earlier only) for implementation defined in define_one_arm_cp_reg_with_opaque()
9281 switch (r->state) { in define_one_arm_cp_reg_with_opaque()
9284 if (r->cp == 0) { in define_one_arm_cp_reg_with_opaque()
9289 if (arm_feature(&cpu->env, ARM_FEATURE_V8) && in define_one_arm_cp_reg_with_opaque()
9290 !arm_feature(&cpu->env, ARM_FEATURE_M)) { in define_one_arm_cp_reg_with_opaque()
9291 assert(r->cp >= 14 && r->cp <= 15); in define_one_arm_cp_reg_with_opaque()
9293 assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15)); in define_one_arm_cp_reg_with_opaque()
9297 assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP); in define_one_arm_cp_reg_with_opaque()
9309 if (r->state != ARM_CP_STATE_AA32) { in define_one_arm_cp_reg_with_opaque()
9311 switch (r->opc1) { in define_one_arm_cp_reg_with_opaque()
9338 /* broken reginfo with out-of-range opc1 */ in define_one_arm_cp_reg_with_opaque()
9342 assert((r->access & ~mask) == 0); in define_one_arm_cp_reg_with_opaque()
9349 if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { in define_one_arm_cp_reg_with_opaque()
9350 if (r->access & PL3_R) { in define_one_arm_cp_reg_with_opaque()
9351 assert((r->fieldoffset || in define_one_arm_cp_reg_with_opaque()
9352 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || in define_one_arm_cp_reg_with_opaque()
9353 r->readfn); in define_one_arm_cp_reg_with_opaque()
9355 if (r->access & PL3_W) { in define_one_arm_cp_reg_with_opaque()
9356 assert((r->fieldoffset || in define_one_arm_cp_reg_with_opaque()
9357 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || in define_one_arm_cp_reg_with_opaque()
9358 r->writefn); in define_one_arm_cp_reg_with_opaque()
9367 if (r->state != state && r->state != ARM_CP_STATE_BOTH) { in define_one_arm_cp_reg_with_opaque()
9370 if ((r->type & ARM_CP_ADD_TLBI_NXS) && in define_one_arm_cp_reg_with_opaque()
9376 * fine-grained trapping. Add the NXS insn here and in define_one_arm_cp_reg_with_opaque()
9383 g_autofree char *name = g_strdup_printf("%sNXS", r->name); in define_one_arm_cp_reg_with_opaque()
9398 * (same for secure and non-secure world) or banked. in define_one_arm_cp_reg_with_opaque()
9402 switch (r->secure) { in define_one_arm_cp_reg_with_opaque()
9406 r->secure, crm, opc1, opc2, in define_one_arm_cp_reg_with_opaque()
9407 r->name); in define_one_arm_cp_reg_with_opaque()
9410 name = g_strdup_printf("%s_S", r->name); in define_one_arm_cp_reg_with_opaque()
9417 crm, opc1, opc2, r->name); in define_one_arm_cp_reg_with_opaque()
9424 * AArch64 registers get mapped to non-secure instance in define_one_arm_cp_reg_with_opaque()
9429 crm, opc1, opc2, r->name); in define_one_arm_cp_reg_with_opaque()
9452 * user-space cannot alter any values and dynamic values pertaining to
9463 if (m->is_glob) { in modify_arm_cp_regs_with_len()
9464 pat = g_pattern_spec_new(m->name); in modify_arm_cp_regs_with_len()
9469 if (pat && g_pattern_match_string(pat, r->name)) { in modify_arm_cp_regs_with_len()
9470 r->type = ARM_CP_CONST; in modify_arm_cp_regs_with_len()
9471 r->access = PL0U_R; in modify_arm_cp_regs_with_len()
9472 r->resetvalue = 0; in modify_arm_cp_regs_with_len()
9474 } else if (strcmp(r->name, m->name) == 0) { in modify_arm_cp_regs_with_len()
9475 r->type = ARM_CP_CONST; in modify_arm_cp_regs_with_len()
9476 r->access = PL0U_R; in modify_arm_cp_regs_with_len()
9477 r->resetvalue &= m->exported_bits; in modify_arm_cp_regs_with_len()
9478 r->resetvalue |= m->fixed_bits; in modify_arm_cp_regs_with_len()
9496 /* Helper coprocessor write function for write-ignore registers */ in arm_cp_write_ignore()
9501 /* Helper coprocessor write function for read-as-zero registers */ in arm_cp_read_zero()
9507 /* Helper coprocessor reset function for do-nothing-on-reset registers */ in arm_cp_reset_ignore()
9520 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || in bad_mode_switch()
9536 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) in bad_mode_switch()
9543 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && in bad_mode_switch()
9560 ZF = (env->ZF == 0); in cpsr_read()
9561 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | in cpsr_read()
9562 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) in cpsr_read()
9563 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) in cpsr_read()
9564 | ((env->condexec_bits & 0xfc) << 8) in cpsr_read()
9565 | (env->GE << 16) | (env->daif & CPSR_AIF); in cpsr_read()
9576 env->ZF = (~val) & CPSR_Z; in cpsr_write()
9577 env->NF = val; in cpsr_write()
9578 env->CF = (val >> 29) & 1; in cpsr_write()
9579 env->VF = (val << 3) & 0x80000000; in cpsr_write()
9582 env->QF = ((val & CPSR_Q) != 0); in cpsr_write()
9585 env->thumb = ((val & CPSR_T) != 0); in cpsr_write()
9588 env->condexec_bits &= ~3; in cpsr_write()
9589 env->condexec_bits |= (val >> 25) & 3; in cpsr_write()
9592 env->condexec_bits &= 3; in cpsr_write()
9593 env->condexec_bits |= (val >> 8) & 0xfc; in cpsr_write()
9596 env->GE = (val >> 16) & 0xf; in cpsr_write()
9602 * whether non-secure software is allowed to change the CPSR_F and CPSR_A in cpsr_write()
9613 changed_daif = (env->daif ^ val) & mask; in cpsr_write()
9618 * abort exceptions from a non-secure state. in cpsr_write()
9620 if (!(env->cp15.scr_el3 & SCR_AW)) { in cpsr_write()
9623 "non-secure world with SCR.AW bit clear\n"); in cpsr_write()
9631 * exceptions from a non-secure state. in cpsr_write()
9633 if (!(env->cp15.scr_el3 & SCR_FW)) { in cpsr_write()
9636 "non-secure world with SCR.FW bit clear\n"); in cpsr_write()
9641 * Check whether non-maskable FIQ (NMFI) support is enabled. in cpsr_write()
9648 "Ignoring attempt to enable CPSR_F flag " in cpsr_write()
9649 "(non-maskable FIQ [NMFI] support enabled)\n"); in cpsr_write()
9655 env->daif &= ~(CPSR_AIF & mask); in cpsr_write()
9656 env->daif |= val & CPSR_AIF & mask; in cpsr_write()
9659 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { in cpsr_write()
9660 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { in cpsr_write()
9687 aarch32_mode_name(env->uncached_cpsr), in cpsr_write()
9694 aarch32_mode_name(env->uncached_cpsr), in cpsr_write()
9695 aarch32_mode_name(val), env->regs[15]); in cpsr_write()
9700 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); in cpsr_write()
9735 old_mode = env->uncached_cpsr & CPSR_M; in switch_mode()
9741 memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); in switch_mode()
9742 memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); in switch_mode()
9744 memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); in switch_mode()
9745 memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); in switch_mode()
9749 env->banked_r13[i] = env->regs[13]; in switch_mode()
9750 env->banked_spsr[i] = env->spsr; in switch_mode()
9753 env->regs[13] = env->banked_r13[i]; in switch_mode()
9754 env->spsr = env->banked_spsr[i]; in switch_mode()
9756 env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; in switch_mode()
9757 env->regs[14] = env->banked_r14[r14_bank_number(mode)]; in switch_mode()
9763 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
9765 * The below multi-dimensional table is used for looking up the target
9772 * | | | | | +--- Current EL
9773 * | | | | +------ Non-secure(0)/Secure(1)
9774 * | | | +--------- HCR mask override
9775 * | | +------------ SCR exec state control
9776 * | +--------------- SCR mask override
9777 * +------------------ 32-bit(0)/64-bit(1) EL3
9780 * 0-3 = EL0-EL3
9781 * -1 = Cannot occur
9795 * BIT IRQ IMO Non-secure Secure
9799 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9800 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
9801 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9802 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
9803 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9804 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
9805 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9806 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
9807 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
9808 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
9809 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
9810 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
9811 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9812 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
9813 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
9814 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
9847 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); in arm_phys_excp_target_el()
9851 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); in arm_phys_excp_target_el()
9855 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); in arm_phys_excp_target_el()
9866 /* Perform a table-lookup for the target EL given the current state */ in arm_phys_excp_target_el()
9876 int idx = cs->exception_index; in arm_log_exception()
9918 idx, exc, cs->cpu_index); in arm_log_exception()
9930 uint32_t mode = env->uncached_cpsr & CPSR_M; in aarch64_sync_32_to_64()
9934 env->xregs[i] = env->regs[i]; in aarch64_sync_32_to_64()
9938 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. in aarch64_sync_32_to_64()
9943 env->xregs[i] = env->usr_regs[i - 8]; in aarch64_sync_32_to_64()
9947 env->xregs[i] = env->regs[i]; in aarch64_sync_32_to_64()
9952 * Registers x13-x23 are the various mode SP and FP registers. Registers in aarch64_sync_32_to_64()
9957 env->xregs[13] = env->regs[13]; in aarch64_sync_32_to_64()
9958 env->xregs[14] = env->regs[14]; in aarch64_sync_32_to_64()
9960 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; in aarch64_sync_32_to_64()
9963 env->xregs[14] = env->regs[14]; in aarch64_sync_32_to_64()
9965 env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; in aarch64_sync_32_to_64()
9970 env->xregs[15] = env->regs[13]; in aarch64_sync_32_to_64()
9972 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; in aarch64_sync_32_to_64()
9976 env->xregs[16] = env->regs[14]; in aarch64_sync_32_to_64()
9977 env->xregs[17] = env->regs[13]; in aarch64_sync_32_to_64()
9979 env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; in aarch64_sync_32_to_64()
9980 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; in aarch64_sync_32_to_64()
9984 env->xregs[18] = env->regs[14]; in aarch64_sync_32_to_64()
9985 env->xregs[19] = env->regs[13]; in aarch64_sync_32_to_64()
9987 env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; in aarch64_sync_32_to_64()
9988 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; in aarch64_sync_32_to_64()
9992 env->xregs[20] = env->regs[14]; in aarch64_sync_32_to_64()
9993 env->xregs[21] = env->regs[13]; in aarch64_sync_32_to_64()
9995 env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; in aarch64_sync_32_to_64()
9996 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; in aarch64_sync_32_to_64()
10000 env->xregs[22] = env->regs[14]; in aarch64_sync_32_to_64()
10001 env->xregs[23] = env->regs[13]; in aarch64_sync_32_to_64()
10003 env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; in aarch64_sync_32_to_64()
10004 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; in aarch64_sync_32_to_64()
10008 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ in aarch64_sync_32_to_64()
10009 * mode, then we can copy from r8-r14. Otherwise, we copy from the in aarch64_sync_32_to_64()
10010 * FIQ bank for r8-r14. in aarch64_sync_32_to_64()
10014 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ in aarch64_sync_32_to_64()
10018 env->xregs[i] = env->fiq_regs[i - 24]; in aarch64_sync_32_to_64()
10020 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; in aarch64_sync_32_to_64()
10021 env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; in aarch64_sync_32_to_64()
10024 env->pc = env->regs[15]; in aarch64_sync_32_to_64()
10035 uint32_t mode = env->uncached_cpsr & CPSR_M; in aarch64_sync_64_to_32()
10039 env->regs[i] = env->xregs[i]; in aarch64_sync_64_to_32()
10043 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. in aarch64_sync_64_to_32()
10044 * Otherwise, we copy x8-x12 into the banked user regs. in aarch64_sync_64_to_32()
10048 env->usr_regs[i - 8] = env->xregs[i]; in aarch64_sync_64_to_32()
10052 env->regs[i] = env->xregs[i]; in aarch64_sync_64_to_32()
10063 env->regs[13] = env->xregs[13]; in aarch64_sync_64_to_32()
10064 env->regs[14] = env->xregs[14]; in aarch64_sync_64_to_32()
10066 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; in aarch64_sync_64_to_32()
10073 env->regs[14] = env->xregs[14]; in aarch64_sync_64_to_32()
10075 env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; in aarch64_sync_64_to_32()
10080 env->regs[13] = env->xregs[15]; in aarch64_sync_64_to_32()
10082 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; in aarch64_sync_64_to_32()
10086 env->regs[14] = env->xregs[16]; in aarch64_sync_64_to_32()
10087 env->regs[13] = env->xregs[17]; in aarch64_sync_64_to_32()
10089 env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; in aarch64_sync_64_to_32()
10090 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; in aarch64_sync_64_to_32()
10094 env->regs[14] = env->xregs[18]; in aarch64_sync_64_to_32()
10095 env->regs[13] = env->xregs[19]; in aarch64_sync_64_to_32()
10097 env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; in aarch64_sync_64_to_32()
10098 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; in aarch64_sync_64_to_32()
10102 env->regs[14] = env->xregs[20]; in aarch64_sync_64_to_32()
10103 env->regs[13] = env->xregs[21]; in aarch64_sync_64_to_32()
10105 env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; in aarch64_sync_64_to_32()
10106 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; in aarch64_sync_64_to_32()
10110 env->regs[14] = env->xregs[22]; in aarch64_sync_64_to_32()
10111 env->regs[13] = env->xregs[23]; in aarch64_sync_64_to_32()
10113 env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; in aarch64_sync_64_to_32()
10114 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; in aarch64_sync_64_to_32()
10118 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ in aarch64_sync_64_to_32()
10119 * mode, then we can copy to r8-r14. Otherwise, we copy to the in aarch64_sync_64_to_32()
10120 * FIQ bank for r8-r14. in aarch64_sync_64_to_32()
10124 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ in aarch64_sync_64_to_32()
10128 env->fiq_regs[i - 24] = env->xregs[i]; in aarch64_sync_64_to_32()
10130 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; in aarch64_sync_64_to_32()
10131 env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; in aarch64_sync_64_to_32()
10134 env->regs[15] = env->pc; in aarch64_sync_64_to_32()
10148 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. in take_aarch32_exception()
10150 env->pstate &= ~PSTATE_SS; in take_aarch32_exception()
10151 env->spsr = cpsr_read(env); in take_aarch32_exception()
10153 env->condexec_bits = 0; in take_aarch32_exception()
10155 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; in take_aarch32_exception()
10161 env->uncached_cpsr &= ~CPSR_E; in take_aarch32_exception()
10162 if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { in take_aarch32_exception()
10163 env->uncached_cpsr |= CPSR_E; in take_aarch32_exception()
10166 env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); in take_aarch32_exception()
10167 env->daif |= mask; in take_aarch32_exception()
10170 if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { in take_aarch32_exception()
10171 env->uncached_cpsr |= CPSR_SSBS; in take_aarch32_exception()
10173 env->uncached_cpsr &= ~CPSR_SSBS; in take_aarch32_exception()
10178 env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; in take_aarch32_exception()
10179 env->elr_el[2] = env->regs[15]; in take_aarch32_exception()
10186 /* ... the target is EL3, from non-secure state. */ in take_aarch32_exception()
10187 env->uncached_cpsr &= ~CPSR_PAN; in take_aarch32_exception()
10194 if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { in take_aarch32_exception()
10195 env->uncached_cpsr |= CPSR_PAN; in take_aarch32_exception()
10205 env->thumb = in take_aarch32_exception()
10208 env->regs[14] = env->regs[15] + offset; in take_aarch32_exception()
10210 env->regs[15] = newpc; in take_aarch32_exception()
10232 CPUARMState *env = &cpu->env; in arm_cpu_do_interrupt_aarch32_hyp()
10234 switch (cs->exception_index) { in arm_cpu_do_interrupt_aarch32_hyp()
10244 env->cp15.ifar_s = env->exception.vaddress; in arm_cpu_do_interrupt_aarch32_hyp()
10246 (uint32_t)env->exception.vaddress); in arm_cpu_do_interrupt_aarch32_hyp()
10250 env->cp15.dfar_s = env->exception.vaddress; in arm_cpu_do_interrupt_aarch32_hyp()
10252 (uint32_t)env->exception.vaddress); in arm_cpu_do_interrupt_aarch32_hyp()
10268 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); in arm_cpu_do_interrupt_aarch32_hyp()
10271 if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { in arm_cpu_do_interrupt_aarch32_hyp()
10274 * QEMU syndrome values are v8-style. v7 has the IL bit in arm_cpu_do_interrupt_aarch32_hyp()
10278 if (cs->exception_index == EXCP_PREFETCH_ABORT || in arm_cpu_do_interrupt_aarch32_hyp()
10279 (cs->exception_index == EXCP_DATA_ABORT && in arm_cpu_do_interrupt_aarch32_hyp()
10280 !(env->exception.syndrome & ARM_EL_ISV)) || in arm_cpu_do_interrupt_aarch32_hyp()
10281 syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { in arm_cpu_do_interrupt_aarch32_hyp()
10282 env->exception.syndrome &= ~ARM_EL_IL; in arm_cpu_do_interrupt_aarch32_hyp()
10285 env->cp15.esr_el[2] = env->exception.syndrome; in arm_cpu_do_interrupt_aarch32_hyp()
10293 if (!(env->cp15.scr_el3 & SCR_EA)) { in arm_cpu_do_interrupt_aarch32_hyp()
10296 if (!(env->cp15.scr_el3 & SCR_IRQ)) { in arm_cpu_do_interrupt_aarch32_hyp()
10299 if (!(env->cp15.scr_el3 & SCR_FIQ)) { in arm_cpu_do_interrupt_aarch32_hyp()
10303 addr += env->cp15.hvbar; in arm_cpu_do_interrupt_aarch32_hyp()
10311 CPUARMState *env = &cpu->env; in arm_cpu_do_interrupt_aarch32()
10319 switch (syn_get_ec(env->exception.syndrome)) { in arm_cpu_do_interrupt_aarch32()
10340 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); in arm_cpu_do_interrupt_aarch32()
10343 if (env->exception.target_el == 2) { in arm_cpu_do_interrupt_aarch32()
10345 switch (syn_get_ec(env->exception.syndrome)) { in arm_cpu_do_interrupt_aarch32()
10350 env->exception.syndrome = syn_insn_abort(arm_current_el(env) == 2, in arm_cpu_do_interrupt_aarch32()
10354 env->exception.syndrome = syn_set_ec(env->exception.syndrome, in arm_cpu_do_interrupt_aarch32()
10358 env->exception.syndrome = syn_set_ec(env->exception.syndrome, in arm_cpu_do_interrupt_aarch32()
10366 switch (cs->exception_index) { in arm_cpu_do_interrupt_aarch32()
10371 if (env->thumb) { in arm_cpu_do_interrupt_aarch32()
10387 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
10388 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
10390 env->exception.fsr, (uint32_t)env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
10397 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
10398 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
10400 env->exception.fsr, in arm_cpu_do_interrupt_aarch32()
10401 (uint32_t)env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
10413 if (env->cp15.scr_el3 & SCR_IRQ) { in arm_cpu_do_interrupt_aarch32()
10424 if (env->cp15.scr_el3 & SCR_FIQ) { in arm_cpu_do_interrupt_aarch32()
10454 env->exception.fsr = arm_fi_to_lfsc(&fi); in arm_cpu_do_interrupt_aarch32()
10456 env->exception.fsr = arm_fi_to_sfsc(&fi); in arm_cpu_do_interrupt_aarch32()
10458 env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000; in arm_cpu_do_interrupt_aarch32()
10459 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
10461 env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
10479 if (env->thumb) { in arm_cpu_do_interrupt_aarch32()
10486 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); in arm_cpu_do_interrupt_aarch32()
10491 addr += env->cp15.mvbar; in arm_cpu_do_interrupt_aarch32()
10499 * This register is only followed in non-monitor mode, and is banked. in arm_cpu_do_interrupt_aarch32()
10505 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { in arm_cpu_do_interrupt_aarch32()
10506 env->cp15.scr_el3 &= ~SCR_NS; in arm_cpu_do_interrupt_aarch32()
10519 int mode = env->uncached_cpsr & CPSR_M; in aarch64_regnum()
10582 ret |= env->pstate & PSTATE_SS; in cpsr_read_for_spsr_elx()
10616 CPUARMState *env = &cpu->env; in arm_cpu_do_interrupt_aarch64()
10617 unsigned int new_el = env->exception.target_el; in arm_cpu_do_interrupt_aarch64()
10618 vaddr addr = env->cp15.vbar_el[new_el]; in arm_cpu_do_interrupt_aarch64()
10667 switch (cs->exception_index) { in arm_cpu_do_interrupt_aarch64()
10670 env->cp15.mfar_el3); in arm_cpu_do_interrupt_aarch64()
10678 if (new_el == 3 && (env->cp15.scr_el3 & SCR_EASE) && in arm_cpu_do_interrupt_aarch64()
10679 syndrome_is_sync_extabt(env->exception.syndrome)) { in arm_cpu_do_interrupt_aarch64()
10682 env->cp15.far_el[new_el] = env->exception.vaddress; in arm_cpu_do_interrupt_aarch64()
10684 env->cp15.far_el[new_el]); in arm_cpu_do_interrupt_aarch64()
10692 switch (syn_get_ec(env->exception.syndrome)) { in arm_cpu_do_interrupt_aarch64()
10700 env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); in arm_cpu_do_interrupt_aarch64()
10709 * number. Notice that we read a 4-bit AArch32 register number and in arm_cpu_do_interrupt_aarch64()
10710 * write back a 5-bit AArch64 one. in arm_cpu_do_interrupt_aarch64()
10712 rt = extract32(env->exception.syndrome, 5, 4); in arm_cpu_do_interrupt_aarch64()
10714 env->exception.syndrome = deposit32(env->exception.syndrome, in arm_cpu_do_interrupt_aarch64()
10720 rt = extract32(env->exception.syndrome, 5, 4); in arm_cpu_do_interrupt_aarch64()
10722 env->exception.syndrome = deposit32(env->exception.syndrome, in arm_cpu_do_interrupt_aarch64()
10724 rt = extract32(env->exception.syndrome, 10, 4); in arm_cpu_do_interrupt_aarch64()
10726 env->exception.syndrome = deposit32(env->exception.syndrome, in arm_cpu_do_interrupt_aarch64()
10730 env->cp15.esr_el[new_el] = env->exception.syndrome; in arm_cpu_do_interrupt_aarch64()
10746 env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff); in arm_cpu_do_interrupt_aarch64()
10747 env->cp15.esr_el[new_el] = env->exception.syndrome; in arm_cpu_do_interrupt_aarch64()
10750 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); in arm_cpu_do_interrupt_aarch64()
10756 env->elr_el[new_el] = env->pc; in arm_cpu_do_interrupt_aarch64()
10773 env->elr_el[new_el] = env->regs[15]; in arm_cpu_do_interrupt_aarch64()
10777 env->condexec_bits = 0; in arm_cpu_do_interrupt_aarch64()
10779 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; in arm_cpu_do_interrupt_aarch64()
10783 env->elr_el[new_el]); in arm_cpu_do_interrupt_aarch64()
10799 if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) { in arm_cpu_do_interrupt_aarch64()
10810 if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { in arm_cpu_do_interrupt_aarch64()
10818 if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPINTMASK)) { in arm_cpu_do_interrupt_aarch64()
10826 env->aarch64 = true; in arm_cpu_do_interrupt_aarch64()
10833 env->pc = addr; in arm_cpu_do_interrupt_aarch64()
10836 new_el, env->pc, pstate_read(env)); in arm_cpu_do_interrupt_aarch64()
10850 CPUARMState *env = &cpu->env; in tcg_handle_semihosting()
10855 env->xregs[0]); in tcg_handle_semihosting()
10857 env->pc += 4; in tcg_handle_semihosting()
10861 env->regs[0]); in tcg_handle_semihosting()
10863 env->regs[15] += env->thumb ? 2 : 4; in tcg_handle_semihosting()
10871 * to the AArch64-entry or AArch32-entry function depending on the
10875 * and KVM to re-inject guest debug exceptions, and to
10876 * inject a Synchronous-External-Abort.
10881 CPUARMState *env = &cpu->env; in arm_cpu_do_interrupt()
10882 unsigned int new_el = env->exception.target_el; in arm_cpu_do_interrupt()
10890 && !excp_is_internal(cs->exception_index)) { in arm_cpu_do_interrupt()
10892 syn_get_ec(env->exception.syndrome), in arm_cpu_do_interrupt()
10893 env->exception.syndrome); in arm_cpu_do_interrupt()
10896 if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { in arm_cpu_do_interrupt()
10908 if (cs->exception_index == EXCP_SEMIHOST) { in arm_cpu_do_interrupt()
10917 * cs->interrupt_request. in arm_cpu_do_interrupt()
10923 assert(!excp_is_internal(cs->exception_index)); in arm_cpu_do_interrupt()
10933 cs->interrupt_request |= CPU_INTERRUPT_EXITTB; in arm_cpu_do_interrupt()
10955 return env->cp15.sctlr_el[el]; in arm_sctlr()
11140 max_tsz = 48 - (gran == Gran64K); in aa64_va_parameters()
11219 * Return the exception level to which FP-disabled exceptions should
11237 if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { in fp_exception_el()
11241 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { in fp_exception_el()
11242 if (!extract32(env->v7m.nsacr, 10, 1)) { in fp_exception_el()
11261 int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); in fp_exception_el()
11284 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode in fp_exception_el()
11285 * to control non-secure access to the FPU. It doesn't have any in fp_exception_el()
11290 if (!extract32(env->cp15.nsacr, 10, 1)) { in fp_exception_el()
11302 switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { in fp_exception_el()
11313 if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { in fp_exception_el()
11320 if (FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TFP)) { in fp_exception_el()
11368 return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); in arm_mmu_idx_el()
11371 /* See ARM pseudo-function ELIsInHost. */ in arm_mmu_idx_el()
11440 assert(vq <= env_archcpu(env)->sve_max_vq); in aarch64_sve_narrow_vq()
11444 memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); in aarch64_sve_narrow_vq()
11450 pmask = ~(-1ULL << (16 * (vq & 3))); in aarch64_sve_narrow_vq()
11454 env->vfp.pregs[i].p[j] &= pmask; in aarch64_sve_narrow_vq()
11503 sm = FIELD_EX64(env->svcr, SVCR, SM); in aarch64_sve_change_el()
11515 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0). in aarch64_sve_change_el()
11516 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition in aarch64_sve_change_el()
11517 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that in aarch64_sve_change_el()
11519 * vq0->vq0 transition between EL0->EL1. in aarch64_sve_change_el()
11539 return arm_secure_to_space(env->v7m.secure); in arm_security_space()
11544 * defined, in which case QEMU defaults to non-secure. in arm_security_space()
11552 if (extract32(env->pstate, 2, 2) == 3) { in arm_security_space()
11560 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { in arm_security_space()
11574 * defined, in which case QEMU defaults to non-secure. in arm_security_space_below_el3()
11585 if (!(env->cp15.scr_el3 & SCR_NS)) { in arm_security_space_below_el3()
11587 } else if (env->cp15.scr_el3 & SCR_NSE) { in arm_security_space_below_el3()