target/arm/helper.c

1749      * If SCR_EL3.{NS,NSE} changes, i.e. change of security state,
2485      * happen when switching EL, can change the effective value of CNTHCTL_EL2
2586          * reset timer to when ISTATUS next has to change
3141      * of software; writing it doesn't actually change the timer frequency.
4262          * With LPAE the TTBCR could result in a change of ASID
4275     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
4318      * A change in VMID to the stage2 page table (Stage2) invalidates
4916      * if we are trying to change any of those then we must
4942      * if we are trying to change any of those then we must
5340      * These bits change the MMU setup:
5723       /* no .writefn needed as this can't cause an ASID change */
5971       /* no .writefn needed as this can't cause an ASID change */
6646     uint64_t change = (env->svcr ^ new) & mask;
6648     if (change == 0) {
6651     env->svcr ^= change;
6653     if (change & R_SVCR_SM_MASK) {
6665     if (change & new & R_SVCR_ZA_MASK) {
8562              * cause the MIDR value to change.
9608      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
9612      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
9623              * Check to see if we are allowed to change the masking of async
9636              * Check to see if we are allowed to change the masking of FIQ
10771                  * If NV2 is disabled, change SPSR when NV,NV1 == 1,0 (I_ZJRNN)
10772                  * If NV2 is enabled, change SPSR when NV is 1 (I_DBTLM)
10921      * Hooks may change global state so BQL should be held, also the
11482  * Notice a change in SVE vector size when changing EL.