target/arm/cpu.h

13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
87 /* The usual mapping for an AArch64 system register to its AArch32
88  * counterpart is for the 32 bit world to have access to the lower
101 /* The 2nd extra word holding syndrome info for data aborts does not use
134 /* CPU state for each instance of a generic timer (in cp15 c14) */
141  * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
142  * For 64-bit, this is a 2048-bit SVE register.
150  *       bits 31..0 for even n, and bits 63..32 for odd n
163  * Align the data for use with TCG host vector operations.
193  * Enum for indexing vfp.fp_status[].
195  * FPST_A32: is the "normal" fp status for AArch32 insns
196  * FPST_A64: is the "normal" fp status for AArch64 insns
197  * FPST_A32_F16: used for AArch32 half-precision calculations
198  * FPST_A64_F16: used for AArch64 half-precision calculations
200  * FPST_STD_F16: used for half-precision
202  * FPST_AH: used for the A64 insns which change behaviour
205  * FPST_AH_F16: used for the A64 insns which change behaviour
208  *       for half-precision
219  * The "standard FPSCR but for fp16 ops" is needed because
221  * using a fixed value for it.
248     /* Regs for current mode.  */
255     /* Regs for A64 mode.  */
258     /* PSTATE isn't an architectural register for ARMv8. However, it is
259      * convenient for us to assemble the underlying state into a 32 bit format
260      * identical to the architectural format used for the SPSR. (This is also
264      *    semantics as for AArch32, as described in the comments on each field)
275     /* Cached TBFLAGS state.  See below for which bits are included.  */
278     /* Frequently accessed CPSR bits are stored separately for efficiency.
293     /* cpsr flag cache for faster execution */
532          * for the access, after which it reverts to the delta value in
572          * a Main Stack Pointer and a Process Stack Pointer for each
576          * and the non-active SP for the current security state in
577          * v7m.other_sp. The stack pointers for the inactive security state
579          * switch_v7m_security_state() is responsible for rearranging them
625         uint32_t target_el; /* EL the exception should be targeted for */
627          * about the intermediate physical address for stage 2 faults.
654         /* Scratch space for aa64 sve predicate temporary.  */
657         /* We store these fpcsr fields separately for convenience.  */
671         /* Scratch space for aa32 neon expansion.  */
684      * Contains the 'val' for the second 64-bit register of LDXP, which comes
722      * is architecturally defined, such that for tiles of elements of esz
784     /* For usermode syscall translation.  */
814 /* These values map onto the return values for
829  * are set for bits in sve_vq_map that have been set by properties.
831  * Bits set in supported represent valid vector lengths for the CPU type.
850     /* For marshalling (mostly coprocessor) register state between the
851      * kernel and QEMU (for KVM) and between two QEMUs (for migration),
862     /* These are used only for migration: incoming data arrives in
882     /* Timer used for WFxT timeouts */
885     /* GPIO outputs for generic timer */
887     /* GPIO output for GICv3 maintenance interrupt signal */
889     /* GPIO output for the PMU interrupt */
892     /* MemoryRegion to use for secure physical accesses */
895     /* MemoryRegion to use for allocation tag accesses */
899     /* For v8M, pointer to the IDAU interface provided by board/SoC */
902     /* 'compatible' string for this CPU for Linux device trees */
905     /* PSCI version for this CPU
945     /* For v8M, initial value of the Secure VTOR */
947     /* For v8M, initial value of the Non-secure VTOR */
950     /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
955     /* KVM init features for this CPU */
982     /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
987     /* The instance init functions for implementation-specific subclasses
994      * is used for reset values of non-constant registers; no reset_
1056     /* The elements of this array are the CCSIDR values for each cache,
1141 /* Callback functions for the generic timer's timers. */
1201  * for when we do direct boot of a guest kernel, and for when we
1233     for (i = 0; i < nr; ++i) {  in sve_bswap64()
1256  * Compute the current vector length for @el & @sm, in units of
1257  * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
1258  * If @sm, compute for SVL, otherwise NVL.
1287  * Functions to register as EL change hooks for PMU mode filtering
1297  * for the current configuration
1303  * for both old and new bit meanings. Code which tests against those
1426 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1442 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1469 /* Mode values for AArch64 */
1482 /* Fields for SMCR_ELx. */
1497 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1696  * For A64 floating point control and status bits are stored in
1699  * For A32 there was only one register, FPSCR. The bits are arranged
1703  * AArch32 view (for FEAT_AFP). Writing the FPSCR leaves these unchanged.
1862 /* V7M CFSR bits for MMFSR */
1870 /* V7M CFSR bits for BFSR */
1879 /* V7M CFSR bits for UFSR */
1930  * define a mask for this and check that it doesn't permit running off
2438      * if the board doesn't set a value, instead of 1GHz. It is for backwards
2456  * of the GPI value, and (except for Root) the concat of NSE:NS.
2472 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */
2596  * "for all purposes other than a direct read or write access of HCR_EL2."
2604  * Function for determining whether guest cp register reads and writes should
2638  * For each register listed in the ARMCPU cpreg_indexes list, write
2653  * @kvm_sync: true if this is for syncing back to KVM
2655  * For each register listed in the ARMCPU cpreg_indexes list, write
2658  * KVM or for outbound migration.
2700  * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2702  * For QEMU, an mmu_idx is not quite the same as a translation regime because:
2706  *  2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2720  *  5. we want to be able to use the TLB for accesses done as part of a
2723  *  6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
2725  *  7. we fold together most secure and non-secure regimes for A-profile,
2726  *     because there are no banked system registers for aarch64, so the
2730  *     because both are in use simultaneously for Secure EL2.
2748  * for a total of 16 different mmu_idx.
2752  * EL2 for cores like the Cortex-R52).
2773  * the same for any particular CPU.
2779  * valid for doing slow path page table walks.
2784  * For M profile we arrange them to have a bit for priv, a bit for negpri
2785  * and a bit for secure.
2791 /* Meanings of the bits for M profile mmu idx values */
2816      * Used for second stage of an S12 page table walk, or for descriptor
2818      * are in use simultaneously for SecureEL2: the security state for
2831      * These are not allocated TLBs and are used only for AT system
2832      * instructions or for the first stage of an S12 page table walk.
2852  * Bit macros for the core-mmu-index values for each index,
2853  * for use when calling tlb_flush_by_mmuidx() and friends.
2936  * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
2942  * flags2 always has 64-bits, even though only 32-bits are used for A32 and M32.
2944  * The bits for 32-bit A-profile and M-profile partially overlap:
2976  * Bit usage when in AArch32 state, for A-profile only.
3003  * Bit usage when in AArch32 state, for M-profile only.
3056  * Helpers for using the above. Note that only the A64 accessors use
3122 /* Return the address space index to use for a memory access */
3128 /* Return the AddressSpace to use for a memory access
3130  * the board gave us a separate AddressSpace for S accesses).
3165  * Rebuild the cached TBFLAGS for arbitrary changed processor state.
3200  * AArch64 usage of the PAGE_TARGET_* bits for linux-user.