target/arm/cpu.h

275     /* Cached TBFLAGS state.  See below for which bits are included.  */
1536  * correspond to TB flags bits cached in the hflags, unless @write_type
2954  * Unless otherwise noted, these bits are cached in env->hflags.
2958 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1)      /* Not cached. */
2972 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8)      /* Not cached. */
2973 FIELD(TBFLAG_AM32, THUMB, 23, 1)         /* Not cached. */
2978 FIELD(TBFLAG_A32, VECLEN, 0, 3)         /* Not cached. */
2979 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2)     /* Not cached. */
2984  * Not cached, because VECLEN+VECSTRIDE are not cached.
2987 FIELD(TBFLAG_A32, VFPEN, 7, 1)         /* Partially cached, minus FPEXC. */
3010 FIELD(TBFLAG_M32, LSPACT, 2, 1)                 /* Not cached. */
3012 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1)     /* Not cached. */
3014 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1)          /* Not cached. */
3016 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1)            /* Not cached. */
3029 FIELD(TBFLAG_A64, BTYPE, 10, 2)         /* Not cached. */
3081  * Return the VL cached within env->hflags, in units of quadwords.
3092  * Return the SVL cached within env->hflags, in units of quadwords.
3165  * Rebuild the cached TBFLAGS for arbitrary changed processor state.