Lines Matching +full:- +full:- +full:disable +full:- +full:capstone
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
22 #include "qemu/qemu-print.h"
25 #include "exec/page-vary.h"
32 #include "exec/translation-block.h"
33 #include "accel/tcg/cpu-ops.h"
36 #include "cpu-features.h"
38 #include "hw/qdev-properties.h"
50 #include "disas/capstone.h"
53 #include "target/arm/cpu-qom.h"
59 CPUARMState *env = &cpu->env; in arm_cpu_set_pc()
62 env->pc = value; in arm_cpu_set_pc()
63 env->thumb = false; in arm_cpu_set_pc()
65 env->regs[15] = value & ~1; in arm_cpu_set_pc()
66 env->thumb = value & 1; in arm_cpu_set_pc()
73 CPUARMState *env = &cpu->env; in arm_cpu_get_pc()
76 return env->pc; in arm_cpu_get_pc()
78 return env->regs[15]; in arm_cpu_get_pc()
94 env->pc = tb->pc; in arm_cpu_synchronize_from_tb()
96 env->regs[15] = tb->pc; in arm_cpu_synchronize_from_tb()
109 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; in arm_restore_state_to_opc()
111 env->pc = data[0]; in arm_restore_state_to_opc()
113 env->condexec_bits = 0; in arm_restore_state_to_opc()
114 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; in arm_restore_state_to_opc()
117 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; in arm_restore_state_to_opc()
119 env->regs[15] = data[0]; in arm_restore_state_to_opc()
121 env->condexec_bits = data[1]; in arm_restore_state_to_opc()
122 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; in arm_restore_state_to_opc()
145 return (cpu->power_state != PSCI_OFF) in arm_cpu_has_work()
146 && cs->interrupt_request & in arm_cpu_has_work()
159 entry->hook = hook; in arm_register_pre_el_change_hook()
160 entry->opaque = opaque; in arm_register_pre_el_change_hook()
162 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); in arm_register_pre_el_change_hook()
170 entry->hook = hook; in arm_register_el_change_hook()
171 entry->opaque = opaque; in arm_register_el_change_hook()
173 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); in arm_register_el_change_hook()
182 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { in cp_reg_reset()
186 if (ri->resetfn) { in cp_reg_reset()
187 ri->resetfn(&cpu->env, ri); in cp_reg_reset()
193 * This is basically only used for fields in non-core coprocessors in cp_reg_reset()
196 if (!ri->fieldoffset) { in cp_reg_reset()
201 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; in cp_reg_reset()
203 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; in cp_reg_reset()
218 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { in cp_reg_check_reset()
222 oldvalue = read_raw_cp_reg(&cpu->env, ri); in cp_reg_check_reset()
224 newvalue = read_raw_cp_reg(&cpu->env, ri); in cp_reg_check_reset()
233 CPUARMState *env = &cpu->env; in arm_cpu_reset_hold()
235 if (acc->parent_phases.hold) { in arm_cpu_reset_hold()
236 acc->parent_phases.hold(obj, type); in arm_cpu_reset_hold()
241 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); in arm_cpu_reset_hold()
242 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); in arm_cpu_reset_hold()
244 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; in arm_cpu_reset_hold()
245 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; in arm_cpu_reset_hold()
246 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; in arm_cpu_reset_hold()
247 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; in arm_cpu_reset_hold()
249 cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON; in arm_cpu_reset_hold()
252 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; in arm_cpu_reset_hold()
257 env->aarch64 = true; in arm_cpu_reset_hold()
259 env->pstate = PSTATE_MODE_EL0t; in arm_cpu_reset_hold()
261 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; in arm_cpu_reset_hold()
263 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | in arm_cpu_reset_hold()
266 env->cp15.sctlr_el[1] |= SCTLR_BT0; in arm_cpu_reset_hold()
269 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; in arm_cpu_reset_hold()
272 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
276 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
278 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; in arm_cpu_reset_hold()
282 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; in arm_cpu_reset_hold()
283 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
285 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; in arm_cpu_reset_hold()
287 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], in arm_cpu_reset_hold()
292 * Enable 48-bit address space (TODO: take reserved_va into account). in arm_cpu_reset_hold()
296 env->cp15.tcr_el[1] = 5 | (1ULL << 37); in arm_cpu_reset_hold()
301 env->cp15.sctlr_el[1] |= SCTLR_ATA0; in arm_cpu_reset_hold()
304 * This corresponds to Linux current->thread.gcr_incl = 0. in arm_cpu_reset_hold()
310 env->cp15.gcr_el1 = 0x1ffff; in arm_cpu_reset_hold()
313 * Disable access to SCXTNUM_EL0 from CSV2_1p2. in arm_cpu_reset_hold()
316 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; in arm_cpu_reset_hold()
317 /* Disable access to Debug Communication Channel (DCC). */ in arm_cpu_reset_hold()
318 env->cp15.mdscr_el1 |= 1 << 12; in arm_cpu_reset_hold()
320 env->cp15.sctlr_el[1] |= SCTLR_MSCEN; in arm_cpu_reset_hold()
324 env->pstate = PSTATE_MODE_EL3h; in arm_cpu_reset_hold()
326 env->pstate = PSTATE_MODE_EL2h; in arm_cpu_reset_hold()
328 env->pstate = PSTATE_MODE_EL1h; in arm_cpu_reset_hold()
332 env->cp15.rvbar = cpu->rvbar_prop; in arm_cpu_reset_hold()
333 env->pc = env->cp15.rvbar; in arm_cpu_reset_hold()
338 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
340 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
344 env->cp15.rvbar = cpu->rvbar_prop; in arm_cpu_reset_hold()
345 env->regs[15] = cpu->rvbar_prop; in arm_cpu_reset_hold()
350 env->uncached_cpsr = ARM_CPU_MODE_USR; in arm_cpu_reset_hold()
352 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; in arm_cpu_reset_hold()
354 env->cp15.c15_cpar = 3; in arm_cpu_reset_hold()
356 env->cp15.c15_cpar = 1; in arm_cpu_reset_hold()
367 env->uncached_cpsr = ARM_CPU_MODE_HYP; in arm_cpu_reset_hold()
369 env->uncached_cpsr = ARM_CPU_MODE_SVC; in arm_cpu_reset_hold()
371 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; in arm_cpu_reset_hold()
378 env->regs[15] = 0xFFFF0000; in arm_cpu_reset_hold()
381 env->vfp.xregs[ARM_VFP_FPEXC] = 0; in arm_cpu_reset_hold()
398 env->v7m.ltpsize = 4; in arm_cpu_reset_hold()
400 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; in arm_cpu_reset_hold()
401 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; in arm_cpu_reset_hold()
405 env->v7m.secure = true; in arm_cpu_reset_hold()
412 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; in arm_cpu_reset_hold()
417 * v8.1M the guest-visible value of NSACR in a CPU without the in arm_cpu_reset_hold()
420 env->v7m.nsacr = 0xcff; in arm_cpu_reset_hold()
427 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; in arm_cpu_reset_hold()
428 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; in arm_cpu_reset_hold()
431 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; in arm_cpu_reset_hold()
432 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; in arm_cpu_reset_hold()
435 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; in arm_cpu_reset_hold()
436 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; in arm_cpu_reset_hold()
440 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; in arm_cpu_reset_hold()
441 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | in arm_cpu_reset_hold()
447 env->regs[14] = 0xffffffff; in arm_cpu_reset_hold()
449 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; in arm_cpu_reset_hold()
450 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; in arm_cpu_reset_hold()
453 vecbase = env->v7m.vecbase[env->v7m.secure]; in arm_cpu_reset_hold()
454 rom = rom_ptr_for_as(cs->as, vecbase, 8); in arm_cpu_reset_hold()
463 * is in non-modifiable memory and this is a second reset after in arm_cpu_reset_hold()
467 initial_msp = ldl_phys(cs->as, vecbase); in arm_cpu_reset_hold()
468 initial_pc = ldl_phys(cs->as, vecbase + 4); in arm_cpu_reset_hold()
475 env->regs[13] = initial_msp & 0xFFFFFFFC; in arm_cpu_reset_hold()
476 env->regs[15] = initial_pc & ~1; in arm_cpu_reset_hold()
477 env->thumb = initial_pc & 1; in arm_cpu_reset_hold()
480 * For user mode we run non-secure and with access to the FPU. in arm_cpu_reset_hold()
482 * and is owned by non-secure. in arm_cpu_reset_hold()
484 env->v7m.secure = false; in arm_cpu_reset_hold()
485 env->v7m.nsacr = 0xcff; in arm_cpu_reset_hold()
486 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; in arm_cpu_reset_hold()
487 env->v7m.fpccr[M_REG_S] &= in arm_cpu_reset_hold()
489 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; in arm_cpu_reset_hold()
500 if (cpu->pmsav7_dregion > 0) { in arm_cpu_reset_hold()
502 memset(env->pmsav8.rbar[M_REG_NS], 0, in arm_cpu_reset_hold()
503 sizeof(*env->pmsav8.rbar[M_REG_NS]) in arm_cpu_reset_hold()
504 * cpu->pmsav7_dregion); in arm_cpu_reset_hold()
505 memset(env->pmsav8.rlar[M_REG_NS], 0, in arm_cpu_reset_hold()
506 sizeof(*env->pmsav8.rlar[M_REG_NS]) in arm_cpu_reset_hold()
507 * cpu->pmsav7_dregion); in arm_cpu_reset_hold()
509 memset(env->pmsav8.rbar[M_REG_S], 0, in arm_cpu_reset_hold()
510 sizeof(*env->pmsav8.rbar[M_REG_S]) in arm_cpu_reset_hold()
511 * cpu->pmsav7_dregion); in arm_cpu_reset_hold()
512 memset(env->pmsav8.rlar[M_REG_S], 0, in arm_cpu_reset_hold()
513 sizeof(*env->pmsav8.rlar[M_REG_S]) in arm_cpu_reset_hold()
514 * cpu->pmsav7_dregion); in arm_cpu_reset_hold()
517 memset(env->pmsav7.drbar, 0, in arm_cpu_reset_hold()
518 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); in arm_cpu_reset_hold()
519 memset(env->pmsav7.drsr, 0, in arm_cpu_reset_hold()
520 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); in arm_cpu_reset_hold()
521 memset(env->pmsav7.dracr, 0, in arm_cpu_reset_hold()
522 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); in arm_cpu_reset_hold()
526 if (cpu->pmsav8r_hdregion > 0) { in arm_cpu_reset_hold()
527 memset(env->pmsav8.hprbar, 0, in arm_cpu_reset_hold()
528 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); in arm_cpu_reset_hold()
529 memset(env->pmsav8.hprlar, 0, in arm_cpu_reset_hold()
530 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); in arm_cpu_reset_hold()
533 env->pmsav7.rnr[M_REG_NS] = 0; in arm_cpu_reset_hold()
534 env->pmsav7.rnr[M_REG_S] = 0; in arm_cpu_reset_hold()
535 env->pmsav8.mair0[M_REG_NS] = 0; in arm_cpu_reset_hold()
536 env->pmsav8.mair0[M_REG_S] = 0; in arm_cpu_reset_hold()
537 env->pmsav8.mair1[M_REG_NS] = 0; in arm_cpu_reset_hold()
538 env->pmsav8.mair1[M_REG_S] = 0; in arm_cpu_reset_hold()
542 if (cpu->sau_sregion > 0) { in arm_cpu_reset_hold()
543 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); in arm_cpu_reset_hold()
544 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); in arm_cpu_reset_hold()
546 env->sau.rnr = 0; in arm_cpu_reset_hold()
548 * the Cortex-M33 does. in arm_cpu_reset_hold()
550 env->sau.ctrl = 0; in arm_cpu_reset_hold()
553 set_flush_to_zero(1, &env->vfp.fp_status[FPST_STD]); in arm_cpu_reset_hold()
554 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]); in arm_cpu_reset_hold()
555 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]); in arm_cpu_reset_hold()
556 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); in arm_cpu_reset_hold()
557 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32]); in arm_cpu_reset_hold()
558 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); in arm_cpu_reset_hold()
559 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); in arm_cpu_reset_hold()
560 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]); in arm_cpu_reset_hold()
561 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); in arm_cpu_reset_hold()
562 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); in arm_cpu_reset_hold()
563 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]); in arm_cpu_reset_hold()
564 set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]); in arm_cpu_reset_hold()
565 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_AH]); in arm_cpu_reset_hold()
566 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]); in arm_cpu_reset_hold()
585 CPUARMState *env = &cpu->env; in arm_emulate_firmware_reset()
618 if (env->aarch64) { in arm_emulate_firmware_reset()
619 env->cp15.scr_el3 |= SCR_RW; in arm_emulate_firmware_reset()
621 env->cp15.scr_el3 |= SCR_API | SCR_APK; in arm_emulate_firmware_reset()
624 env->cp15.scr_el3 |= SCR_ATA; in arm_emulate_firmware_reset()
627 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; in arm_emulate_firmware_reset()
628 env->vfp.zcr_el[3] = 0xf; in arm_emulate_firmware_reset()
631 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; in arm_emulate_firmware_reset()
632 env->cp15.scr_el3 |= SCR_ENTP2; in arm_emulate_firmware_reset()
633 env->vfp.smcr_el[3] = 0xf; in arm_emulate_firmware_reset()
636 env->cp15.scr_el3 |= SCR_HXEN; in arm_emulate_firmware_reset()
639 env->cp15.scr_el3 |= SCR_FGTEN; in arm_emulate_firmware_reset()
645 env->cp15.scr_el3 |= SCR_HCE; in arm_emulate_firmware_reset()
648 /* Put CPU into non-secure state */ in arm_emulate_firmware_reset()
649 env->cp15.scr_el3 |= SCR_NS; in arm_emulate_firmware_reset()
651 env->cp15.nsacr |= 3 << 10; in arm_emulate_firmware_reset()
656 if (env->aarch64) { in arm_emulate_firmware_reset()
657 env->cp15.hcr_el2 |= HCR_RW; in arm_emulate_firmware_reset()
662 if (env->aarch64) { in arm_emulate_firmware_reset()
663 env->pstate = aarch64_pstate_mode(target_el, true); in arm_emulate_firmware_reset()
699 env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) { in arm_excp_unmasked()
700 allIntMask = env->pstate & PSTATE_ALLINT || in arm_excp_unmasked()
701 ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) && in arm_excp_unmasked()
702 (env->pstate & PSTATE_SP)); in arm_excp_unmasked()
723 pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask); in arm_excp_unmasked()
727 pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask); in arm_excp_unmasked()
735 return !(env->daif & PSTATE_F) && (!allIntMask); in arm_excp_unmasked()
741 return !(env->daif & PSTATE_I) && (!allIntMask); in arm_excp_unmasked()
747 return !(env->daif & PSTATE_A); in arm_excp_unmasked()
781 * The old 32-bit-only environment has a more complicated in arm_excp_unmasked()
797 scr = (env->cp15.scr_el3 & SCR_FIQ); in arm_excp_unmasked()
800 * When EL3 is 32-bit, the SCR.FW bit controls whether the in arm_excp_unmasked()
801 * CPSR.F bit masks FIQ interrupts when taken in non-secure in arm_excp_unmasked()
803 * when non-secure but only when FIQs are only routed to EL3. in arm_excp_unmasked()
805 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); in arm_excp_unmasked()
809 * When EL3 execution state is 32-bit, if HCR.IMO is set then in arm_excp_unmasked()
810 * we may override the CPSR.I masking when in non-secure state. in arm_excp_unmasked()
926 env->cp15.hcr_el2 &= ~HCR_VSE; in arm_cpu_exec_interrupt()
934 cs->exception_index = excp_idx; in arm_cpu_exec_interrupt()
935 env->exception.target_el = target_el; in arm_cpu_exec_interrupt()
936 cs->cc->tcg_ops->do_interrupt(cs); in arm_cpu_exec_interrupt()
948 CPUARMState *env = &cpu->env; in arm_cpu_update_virq()
953 (env->irq_line_state & CPU_INTERRUPT_VIRQ); in arm_cpu_update_virq()
955 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { in arm_cpu_update_virq()
970 CPUARMState *env = &cpu->env; in arm_cpu_update_vfiq()
975 (env->irq_line_state & CPU_INTERRUPT_VFIQ); in arm_cpu_update_vfiq()
977 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { in arm_cpu_update_vfiq()
992 CPUARMState *env = &cpu->env; in arm_cpu_update_vinmi()
997 (env->irq_line_state & CPU_INTERRUPT_VINMI); in arm_cpu_update_vinmi()
999 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) { in arm_cpu_update_vinmi()
1013 CPUARMState *env = &cpu->env; in arm_cpu_update_vfnmi()
1019 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) { in arm_cpu_update_vfnmi()
1033 CPUARMState *env = &cpu->env; in arm_cpu_update_vserr()
1036 bool new_state = env->cp15.hcr_el2 & HCR_VSE; in arm_cpu_update_vserr()
1038 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { in arm_cpu_update_vserr()
1051 CPUARMState *env = &cpu->env; in arm_cpu_set_irq()
1073 env->irq_line_state |= mask[irq]; in arm_cpu_set_irq()
1075 env->irq_line_state &= ~mask[irq]; in arm_cpu_set_irq()
1105 CPUARMState *env = &cpu->env; in arm_cpu_virtio_is_big_endian()
1117 /* We're about to come out of WFI/WFE: disable the WFxT timer */ in arm_cpu_exec_halt()
1119 if (cpu->wfxt_timer) { in arm_cpu_exec_halt()
1120 timer_del(cpu->wfxt_timer); in arm_cpu_exec_halt()
1136 * function auto-clears the CPU_INTERRUPT_EXITTB flag for us. in arm_wfxt_timer_cb()
1145 CPUARMState *env = &ac->env; in arm_disas_set_info()
1149 info->cap_arch = CS_ARCH_ARM64; in arm_disas_set_info()
1150 info->cap_insn_unit = 4; in arm_disas_set_info()
1151 info->cap_insn_split = 4; in arm_disas_set_info()
1154 if (env->thumb) { in arm_disas_set_info()
1155 info->cap_insn_unit = 2; in arm_disas_set_info()
1156 info->cap_insn_split = 4; in arm_disas_set_info()
1159 info->cap_insn_unit = 4; in arm_disas_set_info()
1160 info->cap_insn_split = 4; in arm_disas_set_info()
1169 info->cap_arch = CS_ARCH_ARM; in arm_disas_set_info()
1170 info->cap_mode = cap_mode; in arm_disas_set_info()
1173 info->endian = BFD_ENDIAN_LITTLE; in arm_disas_set_info()
1175 info->endian = target_big_endian() ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; in arm_disas_set_info()
1177 info->flags &= ~INSN_ARM_BE32; in arm_disas_set_info()
1180 info->flags |= INSN_ARM_BE32; in arm_disas_set_info()
1188 CPUARMState *env = &cpu->env; in aarch64_cpu_dump_state()
1196 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); in aarch64_cpu_dump_state()
1199 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); in aarch64_cpu_dump_state()
1201 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], in aarch64_cpu_dump_state()
1207 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; in aarch64_cpu_dump_state()
1213 psr & PSTATE_N ? 'N' : '-', in aarch64_cpu_dump_state()
1214 psr & PSTATE_Z ? 'Z' : '-', in aarch64_cpu_dump_state()
1215 psr & PSTATE_C ? 'C' : '-', in aarch64_cpu_dump_state()
1216 psr & PSTATE_V ? 'V' : '-', in aarch64_cpu_dump_state()
1223 env->svcr, in aarch64_cpu_dump_state()
1224 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), in aarch64_cpu_dump_state()
1225 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); in aarch64_cpu_dump_state()
1245 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { in aarch64_cpu_dump_state()
1281 for (j = zcr_len / 4; j >= 0; j--) { in aarch64_cpu_dump_state()
1289 env->vfp.pregs[i].p[j], in aarch64_cpu_dump_state()
1301 i, env->vfp.zregs[i].d[1], in aarch64_cpu_dump_state()
1302 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); in aarch64_cpu_dump_state()
1307 for (j = zcr_len; j >= 0; j--) { in aarch64_cpu_dump_state()
1309 env->vfp.zregs[i].d[j * 2 + 1], in aarch64_cpu_dump_state()
1310 env->vfp.zregs[i].d[j * 2 + 0], in aarch64_cpu_dump_state()
1324 FIELD_EX64(env->svcr, SVCR, ZA) && in aarch64_cpu_dump_state()
1332 for (j = zcr_len; j >= 0; --j) { in aarch64_cpu_dump_state()
1334 env->zarray[i].d[2 * j + 1], in aarch64_cpu_dump_state()
1335 env->zarray[i].d[2 * j], in aarch64_cpu_dump_state()
1345 CPUARMState *env = &cpu->env; in arm_cpu_dump_state()
1354 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); in arm_cpu_dump_state()
1368 ns_status = env->v7m.secure ? "S " : "NS "; in arm_cpu_dump_state()
1374 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { in arm_cpu_dump_state()
1375 mode = "unpriv-thread"; in arm_cpu_dump_state()
1377 mode = "priv-thread"; in arm_cpu_dump_state()
1383 xpsr & XPSR_N ? 'N' : '-', in arm_cpu_dump_state()
1384 xpsr & XPSR_Z ? 'Z' : '-', in arm_cpu_dump_state()
1385 xpsr & XPSR_C ? 'C' : '-', in arm_cpu_dump_state()
1386 xpsr & XPSR_V ? 'V' : '-', in arm_cpu_dump_state()
1396 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; in arm_cpu_dump_state()
1401 psr & CPSR_N ? 'N' : '-', in arm_cpu_dump_state()
1402 psr & CPSR_Z ? 'Z' : '-', in arm_cpu_dump_state()
1403 psr & CPSR_C ? 'C' : '-', in arm_cpu_dump_state()
1404 psr & CPSR_V ? 'V' : '-', in arm_cpu_dump_state()
1426 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); in arm_cpu_dump_state()
1440 return cpu->mp_affinity; in arm_cpu_mp_affinity()
1447 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, in arm_cpu_initfn()
1450 QLIST_INIT(&cpu->pre_el_change_hooks); in arm_cpu_initfn()
1451 QLIST_INIT(&cpu->el_change_hooks); in arm_cpu_initfn()
1456 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. in arm_cpu_initfn()
1461 cpu->sve_default_vq = 4; in arm_cpu_initfn()
1462 cpu->sme_default_vq = 2; in arm_cpu_initfn()
1469 * them to maintain the same interface as non-KVM CPUs. in arm_cpu_initfn()
1476 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, in arm_cpu_initfn()
1477 ARRAY_SIZE(cpu->gt_timer_outputs)); in arm_cpu_initfn()
1479 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, in arm_cpu_initfn()
1480 "gicv3-maintenance-interrupt", 1); in arm_cpu_initfn()
1481 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, in arm_cpu_initfn()
1482 "pmu-interrupt", 1); in arm_cpu_initfn()
1489 cpu->dtb_compatible = "qemu,unknown"; in arm_cpu_initfn()
1490 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ in arm_cpu_initfn()
1491 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; in arm_cpu_initfn()
1495 cpu->psci_version = QEMU_PSCI_VERSION_1_1; in arm_cpu_initfn()
1507 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
1510 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
1527 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true);
1536 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1539 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1544 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1552 return cpu->has_pmu; in arm_get_pmu()
1564 set_feature(&cpu->env, ARM_FEATURE_PMU); in arm_set_pmu()
1566 unset_feature(&cpu->env, ARM_FEATURE_PMU); in arm_set_pmu()
1568 cpu->has_pmu = value; in arm_set_pmu()
1575 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_cpu_get_aarch64()
1590 "unless KVM is enabled and 32-bit EL1 " in aarch64_cpu_set_aarch64()
1594 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_cpu_set_aarch64()
1596 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_cpu_set_aarch64()
1605 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, in gt_cntfrq_period_ns()
1613 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to in gt_cntfrq_period_ns()
1620 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? in gt_cntfrq_period_ns()
1621 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; in gt_cntfrq_period_ns()
1626 CPUARMState *env = &cpu->env; in arm_cpu_propagate_feature_implications()
1652 * for TCG would a consistency-check failure be a QEMU bug. in arm_cpu_propagate_feature_implications()
1654 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { in arm_cpu_propagate_feature_implications()
1662 * For QEMU, for backwards-compatibility we implement some in arm_cpu_propagate_feature_implications()
1685 * non-EL3 configs. This is needed by some legacy boards. in arm_cpu_propagate_feature_implications()
1727 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { in arm_cpu_post_init()
1731 "Set on/off to enable/disable aarch64 " in arm_cpu_post_init()
1734 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || in arm_cpu_post_init()
1735 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { in arm_cpu_post_init()
1739 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { in arm_cpu_post_init()
1743 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { in arm_cpu_post_init()
1745 &cpu->rvbar_prop, in arm_cpu_post_init()
1750 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { in arm_cpu_post_init()
1756 object_property_add_link(obj, "secure-memory", in arm_cpu_post_init()
1758 (Object **)&cpu->secure_memory, in arm_cpu_post_init()
1763 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { in arm_cpu_post_init()
1768 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { in arm_cpu_post_init()
1769 cpu->has_pmu = true; in arm_cpu_post_init()
1774 * Allow user to turn off VFP and Neon support, but only for TCG -- in arm_cpu_post_init()
1778 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { in arm_cpu_post_init()
1780 cpu->has_vfp = true; in arm_cpu_post_init()
1781 cpu->has_vfp_d32 = true; in arm_cpu_post_init()
1788 cpu->has_vfp = true; in arm_cpu_post_init()
1794 cpu->has_vfp_d32 = true; in arm_cpu_post_init()
1797 * Armv8-A are either 0b0000 and 0b0010. On such CPUs, in arm_cpu_post_init()
1801 && !(arm_feature(&cpu->env, ARM_FEATURE_V8) in arm_cpu_post_init()
1802 && !arm_feature(&cpu->env, ARM_FEATURE_M))) { in arm_cpu_post_init()
1809 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { in arm_cpu_post_init()
1810 cpu->has_neon = true; in arm_cpu_post_init()
1816 if (arm_feature(&cpu->env, ARM_FEATURE_M) && in arm_cpu_post_init()
1817 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { in arm_cpu_post_init()
1821 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { in arm_cpu_post_init()
1823 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { in arm_cpu_post_init()
1829 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { in arm_cpu_post_init()
1830 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, in arm_cpu_post_init()
1838 object_property_add_uint32_ptr(obj, "init-svtor", in arm_cpu_post_init()
1839 &cpu->init_svtor, in arm_cpu_post_init()
1842 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { in arm_cpu_post_init()
1847 object_property_add_uint32_ptr(obj, "init-nsvtor", in arm_cpu_post_init()
1848 &cpu->init_nsvtor, in arm_cpu_post_init()
1853 object_property_add_uint32_ptr(obj, "psci-conduit", in arm_cpu_post_init()
1854 &cpu->psci_conduit, in arm_cpu_post_init()
1859 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { in arm_cpu_post_init()
1868 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && in arm_cpu_post_init()
1870 object_property_add_link(obj, "tag-memory", in arm_cpu_post_init()
1872 (Object **)&cpu->tag_memory, in arm_cpu_post_init()
1876 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { in arm_cpu_post_init()
1877 object_property_add_link(obj, "secure-tag-memory", in arm_cpu_post_init()
1879 (Object **)&cpu->secure_tag_memory, in arm_cpu_post_init()
1892 g_hash_table_destroy(cpu->cp_regs); in arm_cpu_finalizefn()
1894 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { in arm_cpu_finalizefn()
1898 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { in arm_cpu_finalizefn()
1903 if (cpu->pmu_timer) { in arm_cpu_finalizefn()
1904 timer_free(cpu->pmu_timer); in arm_cpu_finalizefn()
1906 if (cpu->wfxt_timer) { in arm_cpu_finalizefn()
1907 timer_free(cpu->wfxt_timer); in arm_cpu_finalizefn()
1916 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { in arm_cpu_finalize_features()
1966 CPUARMState *env = &cpu->env; in arm_cpu_realizefn()
1970 /* Use pc-relative instructions in system-mode */ in arm_cpu_realizefn()
1978 if (cpu->host_cpu_probe_failed) { in arm_cpu_realizefn()
1987 if (!cpu->gt_cntfrq_hz) { in arm_cpu_realizefn()
1995 * We will use the back-compat value: in arm_cpu_realizefn()
1996 * - for QEMU CPU types added before we standardized on 1GHz in arm_cpu_realizefn()
1997 * - for versioned machine types with a version of 9.0 or earlier in arm_cpu_realizefn()
2000 cpu->backcompat_cntfrq) { in arm_cpu_realizefn()
2001 cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ; in arm_cpu_realizefn()
2003 cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; in arm_cpu_realizefn()
2008 /* The NVIC and M-profile CPU are two halves of a single piece of in arm_cpu_realizefn()
2013 if (!env->nvic) { in arm_cpu_realizefn()
2014 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); in arm_cpu_realizefn()
2018 if (env->nvic) { in arm_cpu_realizefn()
2019 error_setg(errp, "This board can only be used with Cortex-M CPUs"); in arm_cpu_realizefn()
2036 "Cannot enable %s when using an M-profile guest CPU", in arm_cpu_realizefn()
2040 if (cpu->has_el3) { in arm_cpu_realizefn()
2046 if (cpu->tag_memory) { in arm_cpu_realizefn()
2057 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, in arm_cpu_realizefn()
2059 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, in arm_cpu_realizefn()
2061 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, in arm_cpu_realizefn()
2063 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, in arm_cpu_realizefn()
2065 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, in arm_cpu_realizefn()
2067 cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, in arm_cpu_realizefn()
2069 cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, in arm_cpu_realizefn()
2089 * dual-mapped code. in arm_cpu_realizefn()
2094 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); in arm_cpu_realizefn()
2098 cpu->has_vfp != cpu->has_neon) { in arm_cpu_realizefn()
2101 * more flexible and permits VFP-no-Neon and Neon-no-VFP. in arm_cpu_realizefn()
2108 if (cpu->has_vfp_d32 != cpu->has_neon) { in arm_cpu_realizefn()
2109 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); in arm_cpu_realizefn()
2113 if (!cpu->has_vfp_d32) { in arm_cpu_realizefn()
2116 u = cpu->isar.mvfr0; in arm_cpu_realizefn()
2118 cpu->isar.mvfr0 = u; in arm_cpu_realizefn()
2121 if (!cpu->has_vfp) { in arm_cpu_realizefn()
2125 t = cpu->isar.id_aa64isar1; in arm_cpu_realizefn()
2127 cpu->isar.id_aa64isar1 = t; in arm_cpu_realizefn()
2129 t = cpu->isar.id_aa64pfr0; in arm_cpu_realizefn()
2131 cpu->isar.id_aa64pfr0 = t; in arm_cpu_realizefn()
2133 u = cpu->isar.id_isar6; in arm_cpu_realizefn()
2136 cpu->isar.id_isar6 = u; in arm_cpu_realizefn()
2138 u = cpu->isar.mvfr0; in arm_cpu_realizefn()
2148 cpu->isar.mvfr0 = u; in arm_cpu_realizefn()
2150 u = cpu->isar.mvfr1; in arm_cpu_realizefn()
2157 cpu->isar.mvfr1 = u; in arm_cpu_realizefn()
2159 u = cpu->isar.mvfr2; in arm_cpu_realizefn()
2161 cpu->isar.mvfr2 = u; in arm_cpu_realizefn()
2164 if (!cpu->has_neon) { in arm_cpu_realizefn()
2170 t = cpu->isar.id_aa64isar0; in arm_cpu_realizefn()
2178 cpu->isar.id_aa64isar0 = t; in arm_cpu_realizefn()
2180 t = cpu->isar.id_aa64isar1; in arm_cpu_realizefn()
2184 cpu->isar.id_aa64isar1 = t; in arm_cpu_realizefn()
2186 t = cpu->isar.id_aa64pfr0; in arm_cpu_realizefn()
2188 cpu->isar.id_aa64pfr0 = t; in arm_cpu_realizefn()
2190 u = cpu->isar.id_isar5; in arm_cpu_realizefn()
2196 cpu->isar.id_isar5 = u; in arm_cpu_realizefn()
2198 u = cpu->isar.id_isar6; in arm_cpu_realizefn()
2203 cpu->isar.id_isar6 = u; in arm_cpu_realizefn()
2206 u = cpu->isar.mvfr1; in arm_cpu_realizefn()
2211 cpu->isar.mvfr1 = u; in arm_cpu_realizefn()
2213 u = cpu->isar.mvfr2; in arm_cpu_realizefn()
2215 cpu->isar.mvfr2 = u; in arm_cpu_realizefn()
2219 if (!cpu->has_neon && !cpu->has_vfp) { in arm_cpu_realizefn()
2223 t = cpu->isar.id_aa64isar0; in arm_cpu_realizefn()
2225 cpu->isar.id_aa64isar0 = t; in arm_cpu_realizefn()
2227 t = cpu->isar.id_aa64isar1; in arm_cpu_realizefn()
2229 cpu->isar.id_aa64isar1 = t; in arm_cpu_realizefn()
2231 u = cpu->isar.mvfr0; in arm_cpu_realizefn()
2233 cpu->isar.mvfr0 = u; in arm_cpu_realizefn()
2236 u = cpu->isar.mvfr1; in arm_cpu_realizefn()
2238 cpu->isar.mvfr1 = u; in arm_cpu_realizefn()
2241 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { in arm_cpu_realizefn()
2246 u = cpu->isar.id_isar1; in arm_cpu_realizefn()
2248 cpu->isar.id_isar1 = u; in arm_cpu_realizefn()
2250 u = cpu->isar.id_isar2; in arm_cpu_realizefn()
2253 cpu->isar.id_isar2 = u; in arm_cpu_realizefn()
2255 u = cpu->isar.id_isar3; in arm_cpu_realizefn()
2258 cpu->isar.id_isar3 = u; in arm_cpu_realizefn()
2301 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. in arm_cpu_realizefn()
2306 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { in arm_cpu_realizefn()
2307 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index, in arm_cpu_realizefn()
2311 if (cpu->reset_hivecs) { in arm_cpu_realizefn()
2312 cpu->reset_sctlr |= (1 << 13); in arm_cpu_realizefn()
2315 if (cpu->cfgend) { in arm_cpu_realizefn()
2317 cpu->reset_sctlr |= SCTLR_EE; in arm_cpu_realizefn()
2319 cpu->reset_sctlr |= SCTLR_B; in arm_cpu_realizefn()
2323 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { in arm_cpu_realizefn()
2324 /* If the has_el3 CPU property is disabled then we need to disable the in arm_cpu_realizefn()
2330 * Disable the security extension feature bits in the processor in arm_cpu_realizefn()
2333 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); in arm_cpu_realizefn()
2334 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); in arm_cpu_realizefn()
2335 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, in arm_cpu_realizefn()
2338 /* Disable the realm management extension, which requires EL3. */ in arm_cpu_realizefn()
2339 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, in arm_cpu_realizefn()
2343 if (!cpu->has_el2) { in arm_cpu_realizefn()
2347 if (!cpu->has_pmu) { in arm_cpu_realizefn()
2359 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, in arm_cpu_realizefn()
2363 cpu->isar.id_aa64dfr0 = in arm_cpu_realizefn()
2364 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); in arm_cpu_realizefn()
2365 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); in arm_cpu_realizefn()
2366 cpu->pmceid0 = 0; in arm_cpu_realizefn()
2367 cpu->pmceid1 = 0; in arm_cpu_realizefn()
2372 * Disable the hypervisor feature bits in the processor feature in arm_cpu_realizefn()
2375 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, in arm_cpu_realizefn()
2377 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, in arm_cpu_realizefn()
2383 * The architectural range of GM blocksize is 2-6, however qemu in arm_cpu_realizefn()
2387 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); in arm_cpu_realizefn()
2392 * If we run with TCG and do not have tag-memory provided by in arm_cpu_realizefn()
2394 * This matches Cortex-A710 BROADCASTMTE input being LOW. in arm_cpu_realizefn()
2396 if (tcg_enabled() && cpu->tag_memory == NULL) { in arm_cpu_realizefn()
2397 cpu->isar.id_aa64pfr1 = in arm_cpu_realizefn()
2398 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); in arm_cpu_realizefn()
2405 if (kvm_enabled() && !cpu->kvm_mte) { in arm_cpu_realizefn()
2406 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); in arm_cpu_realizefn()
2413 cpu->wfxt_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in arm_cpu_realizefn()
2423 * try to access the non-existent system registers for them. in arm_cpu_realizefn()
2426 cpu->isar.id_aa64dfr0 = in arm_cpu_realizefn()
2427 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); in arm_cpu_realizefn()
2429 cpu->isar.id_aa64dfr0 = in arm_cpu_realizefn()
2430 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); in arm_cpu_realizefn()
2431 /* FEAT_TRF (Self-hosted Trace Extension) */ in arm_cpu_realizefn()
2432 cpu->isar.id_aa64dfr0 = in arm_cpu_realizefn()
2433 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); in arm_cpu_realizefn()
2434 cpu->isar.id_dfr0 = in arm_cpu_realizefn()
2435 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); in arm_cpu_realizefn()
2437 cpu->isar.id_aa64dfr0 = in arm_cpu_realizefn()
2438 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); in arm_cpu_realizefn()
2439 cpu->isar.id_dfr0 = in arm_cpu_realizefn()
2440 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); in arm_cpu_realizefn()
2442 cpu->isar.id_dfr0 = in arm_cpu_realizefn()
2443 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); in arm_cpu_realizefn()
2445 cpu->isar.id_aa64pfr0 = in arm_cpu_realizefn()
2446 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); in arm_cpu_realizefn()
2447 cpu->isar.id_pfr0 = in arm_cpu_realizefn()
2448 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); in arm_cpu_realizefn()
2450 cpu->isar.id_aa64pfr0 = in arm_cpu_realizefn()
2451 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); in arm_cpu_realizefn()
2454 /* MPU can be configured out of a PMSA CPU either by setting has-mpu in arm_cpu_realizefn()
2455 * to false or by setting pmsav7-dregion to 0. in arm_cpu_realizefn()
2457 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { in arm_cpu_realizefn()
2458 cpu->has_mpu = false; in arm_cpu_realizefn()
2459 cpu->pmsav7_dregion = 0; in arm_cpu_realizefn()
2460 cpu->pmsav8r_hdregion = 0; in arm_cpu_realizefn()
2465 uint32_t nr = cpu->pmsav7_dregion; in arm_cpu_realizefn()
2475 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); in arm_cpu_realizefn()
2476 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); in arm_cpu_realizefn()
2478 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); in arm_cpu_realizefn()
2479 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); in arm_cpu_realizefn()
2482 env->pmsav7.drbar = g_new0(uint32_t, nr); in arm_cpu_realizefn()
2483 env->pmsav7.drsr = g_new0(uint32_t, nr); in arm_cpu_realizefn()
2484 env->pmsav7.dracr = g_new0(uint32_t, nr); in arm_cpu_realizefn()
2488 if (cpu->pmsav8r_hdregion > 0xff) { in arm_cpu_realizefn()
2490 cpu->pmsav8r_hdregion); in arm_cpu_realizefn()
2494 if (cpu->pmsav8r_hdregion) { in arm_cpu_realizefn()
2495 env->pmsav8.hprbar = g_new0(uint32_t, in arm_cpu_realizefn()
2496 cpu->pmsav8r_hdregion); in arm_cpu_realizefn()
2497 env->pmsav8.hprlar = g_new0(uint32_t, in arm_cpu_realizefn()
2498 cpu->pmsav8r_hdregion); in arm_cpu_realizefn()
2503 uint32_t nr = cpu->sau_sregion; in arm_cpu_realizefn()
2511 env->sau.rbar = g_new0(uint32_t, nr); in arm_cpu_realizefn()
2512 env->sau.rlar = g_new0(uint32_t, nr); in arm_cpu_realizefn()
2534 unsigned int smp_cpus = ms->smp.cpus; in arm_cpu_realizefn()
2535 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); in arm_cpu_realizefn()
2538 * We must set cs->num_ases to the final value before in arm_cpu_realizefn()
2541 if (cpu->tag_memory != NULL) { in arm_cpu_realizefn()
2542 cs->num_ases = 3 + has_secure; in arm_cpu_realizefn()
2544 cs->num_ases = 1 + has_secure; in arm_cpu_realizefn()
2548 if (!cpu->secure_memory) { in arm_cpu_realizefn()
2549 cpu->secure_memory = cs->memory; in arm_cpu_realizefn()
2551 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", in arm_cpu_realizefn()
2552 cpu->secure_memory); in arm_cpu_realizefn()
2555 if (cpu->tag_memory != NULL) { in arm_cpu_realizefn()
2556 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", in arm_cpu_realizefn()
2557 cpu->tag_memory); in arm_cpu_realizefn()
2559 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", in arm_cpu_realizefn()
2560 cpu->secure_tag_memory); in arm_cpu_realizefn()
2564 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); in arm_cpu_realizefn()
2567 if (cpu->core_count == -1) { in arm_cpu_realizefn()
2568 cpu->core_count = smp_cpus; in arm_cpu_realizefn()
2573 int dcz_blocklen = 4 << cpu->dcz_blocksize; in arm_cpu_realizefn()
2579 * is variable and, for compatibility with -machine virt-2.7, in arm_cpu_realizefn()
2599 acc->parent_realize(dev, errp); in arm_cpu_realizefn()
2612 /* For backwards compatibility usermode emulation allows "-cpu any", in arm_cpu_class_by_name()
2613 * which has the same semantics as "-cpu max". in arm_cpu_class_by_name()
2629 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2631 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2632 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2633 /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
2634 DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
2635 DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU,
2642 CPUARMState *env = &cpu->env; in arm_gdb_arch_name()
2656 CPUARMState *env = &cpu->env; in arm_gdb_get_core_xml_file()
2659 return "aarch64-core.xml"; in arm_gdb_get_core_xml_file()
2662 return "arm-m-profile.xml"; in arm_gdb_get_core_xml_file()
2664 return "arm-core.xml"; in arm_gdb_get_core_xml_file()
2675 * include/exec/cpu_ldst.h, and not some place linux-user specific.
2677 * Note that arm-*-user will never set tagged_addr_enable.
2682 if (env->tagged_addr_enable) { in aarch64_untagged_addr()
2692 #include "hw/core/sysemu-cpu-ops.h"
2713 * Double check that we're not truncating a 40-bit physical address. in aprofile_pointer_wrap()
2770 &acc->parent_realize); in arm_cpu_class_init()
2775 &acc->parent_phases); in arm_cpu_class_init()
2777 cc->class_by_name = arm_cpu_class_by_name; in arm_cpu_class_init()
2778 cc->dump_state = arm_cpu_dump_state; in arm_cpu_class_init()
2779 cc->set_pc = arm_cpu_set_pc; in arm_cpu_class_init()
2780 cc->get_pc = arm_cpu_get_pc; in arm_cpu_class_init()
2781 cc->gdb_read_register = arm_cpu_gdb_read_register; in arm_cpu_class_init()
2782 cc->gdb_write_register = arm_cpu_gdb_write_register; in arm_cpu_class_init()
2784 cc->sysemu_ops = &arm_sysemu_ops; in arm_cpu_class_init()
2786 cc->gdb_arch_name = arm_gdb_arch_name; in arm_cpu_class_init()
2787 cc->gdb_get_core_xml_file = arm_gdb_get_core_xml_file; in arm_cpu_class_init()
2788 cc->gdb_stop_before_watchpoint = true; in arm_cpu_class_init()
2789 cc->disas_set_info = arm_disas_set_info; in arm_cpu_class_init()
2792 cc->tcg_ops = &arm_tcg_ops; in arm_cpu_class_init()
2800 acc->info->initfn(obj); in arm_cpu_instance_init()
2809 acc->info = data; in cpu_register_class_init()
2810 if (acc->info->deprecation_note) { in cpu_register_class_init()
2811 cc->deprecation_note = acc->info->deprecation_note; in cpu_register_class_init()
2820 .class_init = info->class_init ?: cpu_register_class_init, in arm_cpu_register()
2824 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); in arm_cpu_register()