Lines Matching +full:alpha +full:- +full:linux +full:- +full:user
2 * Alpha emulation cpu definitions for qemu.
23 #include "cpu-qom.h"
24 #include "exec/cpu-common.h"
25 #include "exec/cpu-defs.h"
26 #include "exec/cpu-interrupt.h"
27 #include "qemu/cpu-float.h"
32 /* Alpha major type */
110 /* IEEE floating-point operations encoding */
128 /* FPCR bits -- right-shifted 32 so we can use a uint32_t. */
129 #define FPCR_SUM (1U << (63 - 32))
130 #define FPCR_INED (1U << (62 - 32))
131 #define FPCR_UNFD (1U << (61 - 32))
132 #define FPCR_UNDZ (1U << (60 - 32))
133 #define FPCR_DYN_SHIFT (58 - 32)
139 #define FPCR_IOV (1U << (57 - 32))
140 #define FPCR_INE (1U << (56 - 32))
141 #define FPCR_UNF (1U << (55 - 32))
142 #define FPCR_OVF (1U << (54 - 32))
143 #define FPCR_DZE (1U << (53 - 32))
144 #define FPCR_INV (1U << (52 - 32))
145 #define FPCR_OVFD (1U << (51 - 32))
146 #define FPCR_DZED (1U << (50 - 32))
147 #define FPCR_INVD (1U << (49 - 32))
148 #define FPCR_DNZ (1U << (48 - 32))
149 #define FPCR_DNOD (1U << (47 - 32))
155 has read-as-zero bits in the FPCR when the features aren't implemented.
163 #define SWCR_TRAP_ENABLE_MASK ((1U << 7) - (1U << 1))
175 #define SWCR_STATUS_MASK ((1U << 23) - (1U << 17))
183 /* Alpha has 5 MMU modes: PALcode, Kernel, Executive, Supervisor, and User.
184 The Unix PALcode only exposes the kernel and user modes; presumably
189 or via an os-installed "alternate mode", which is one of the 4 above.
222 /* The high 32-bits of the processor cycle counter. */
227 emulation and user-mode. */
258 * An Alpha CPU.
273 * An Alpha CPU model.
313 /* Alpha-specific interrupt pending bits. */
368 /* CPUAlphaState->flags constants. These are laid out so that we
389 int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; in alpha_env_mmu_index()
390 if (env->flags & ENV_FLAG_PAL_MODE) { in alpha_env_mmu_index()
468 /* Copied from linux ieee_swcr_to_fpcr. */
486 /* Copied from linux ieee_fpcr_to_swcr. */