pl011/src/registers.rs

3 // SPDX-License-Identifier: GPL-2.0-or-later
19 #[derive(Debug, Eq, PartialEq, qemu_api_macros::TryInto)]
40     /// `IrDA` Low-Power Counter Register
94 /// read for RX. It is a 12-bit register, where bits 7..0 are the
107     // bilge is not very const-friendly, unfortunately
142     fn default() -> Self {  in default()
151 /// This has the usual inbound RS232 modem-control signals, plus flags
185     fn default() -> Self {  in default()
201     /// PEN: Parity enable
207     /// FEN: Enable FIFOs
217     /// 31:8 - Reserved, do not modify, read as zero.
230     fn default() -> Self {  in default()
236 #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)]
245 #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)]
246 /// `FEN` "Enable FIFOs" or Device mode, field of [Line Control
250     /// 1-byte-deep holding registers
257 #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)]
276 /// enable bits, and the bits to write to set the usual outbound RS232
282     /// `UARTEN` UART enable: 0 = UART is disabled.
284     /// `SIREN` `SIR` enable: disable or enable IrDA SIR ENDEC.
287     /// `SIRLP` SIR low-power IrDA mode. QEMU does not model this.
291     /// `LBE` Loopback enable: feed UART output back to the input
293     /// `TXE` Transmit enable
295     /// `RXE` Receive enable
305     /// `RTSEn` RTS hardware flow control enable
307     /// `CTSEn` CTS hardware flow control enable
309     /// 31:16 - Reserved, do not modify, read as zero.
323     fn default() -> Self {  in default()