linux-headers/linux/iommufd.h

1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES.
23  *  - ENOTTY: The IOCTL number itself is not supported at all
24  *  - E2BIG: The IOCTL number is supported, but the provided structure has
25  *    non-zero in a part the kernel does not understand.
26  *  - EOPNOTSUPP: The IOCTL number is supported, and the structure is
29  *  - EINVAL: Everything about the IOCTL was understood, but a field is not
31  *  - ENOENT: An ID or IOVA provided does not exist.
32  *  - ENOMEM: Out of memory.
33  *  - EOVERFLOW: Mathematics overflowed.
62  * struct iommu_destroy - ioctl(IOMMU_DESTROY)
75  * struct iommu_ioas_alloc - ioctl(IOMMU_IOAS_ALLOC)
91  * struct iommu_iova_range - ioctl(IOMMU_IOVA_RANGE)
103  * struct iommu_ioas_iova_ranges - ioctl(IOMMU_IOAS_IOVA_RANGES)
115  * The allowed ranges are dependent on the HW path the DMA operation takes, and
123  * the total number of iovas filled in. The ioctl will return -EMSGSIZE and set
125  * caller should allocate a larger output array and re-issue the ioctl.
147  * struct iommu_ioas_allow_iovas - ioctl(IOMMU_IOAS_ALLOW_IOVAS)
179  * enum iommufd_ioas_map_flags - Flags for map and copy
182  * @IOMMU_IOAS_MAP_WRITEABLE: DMA is allowed to write to this mapping
183  * @IOMMU_IOAS_MAP_READABLE: DMA is allowed to read from this mapping
192  * struct iommu_ioas_map - ioctl(IOMMU_IOAS_MAP)
222  * struct iommu_ioas_map_file - ioctl(IOMMU_IOAS_MAP_FILE)
246  * struct iommu_ioas_copy - ioctl(IOMMU_IOAS_COPY)
277  * struct iommu_ioas_unmap - ioctl(IOMMU_IOAS_UNMAP)
297  * enum iommufd_option - ioctl(IOMMU_OPTION_RLIMIT_MODE) and
306  *    PAGE_SIZE. This can be useful for benchmarking.  This is a per-IOAS
315  * enum iommufd_option_ops - ioctl(IOMMU_OPTION_OP_SET) and
326  * struct iommu_option - iommu option multiplexer
349  * enum iommufd_vfio_ioas_op - IOMMU_VFIO_IOAS_* ioctls
361  * struct iommu_vfio_ioas - ioctl(IOMMU_VFIO_IOAS)
373  * this ioctl. SET or CLEAR does not destroy any auto-created IOAS.
384  * enum iommufd_hwpt_alloc_flags - Flags for HWPT allocation
391  * @IOMMU_HWPT_ALLOC_PASID: Requests a domain that can be used with PASID. The
393  *                          Any domain attached to the non-PASID part of the
397  *                          not recommended for both the non-PASID part
400  *                          error (-EOPNOTSUPP).
410  * enum iommu_hwpt_vtd_s1_flags - Intel VT-d stage-1 page table
423  * struct iommu_hwpt_vtd_s1 - Intel VT-d stage-1 page table
426  * @pgtbl_addr: The base address of the stage-1 page table.
427  * @addr_width: The address width of the stage-1 page table
438  * struct iommu_hwpt_arm_smmuv3 - ARM SMMUv3 nested STE
442  *       the translation. Must be little-endian.
444  *       - word-0: V, Cfg, S1Fmt, S1ContextPtr, S1CDMax
445  *       - word-1: EATS, S1DSS, S1CIR, S1COR, S1CSH, S1STALLD
447  * -EIO will be returned if @ste is not legal or contains any non-allowed field.
458  * enum iommu_hwpt_data_type - IOMMU HWPT Data Type
460  * @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table
470  * struct iommu_hwpt_alloc - ioctl(IOMMU_HWPT_ALLOC)
482  * @__reserved2: Padding to 64-bit alignment. Must be 0.
488  * A kernel-managed HWPT will be created with the mappings from the given
493  * A user-managed nested HWPT will be created from a given vIOMMU (wrapping a
496  * case, the @data_type must be set to a pre-defined type corresponding to an
521  * enum iommu_hw_info_vtd_flags - Flags for VT-d hw_info
522  * @IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17: If set, disallow read-only mappings
524 …                 https://www.intel.com/content/www/us/en/content-details/772415/content-details.ht…
531  * struct iommu_hw_info_vtd - Intel VT-d hardware information
536  * @cap_reg: Value of Intel VT-d capability register defined in VT-d spec
538  * @ecap_reg: Value of Intel VT-d capability register defined in VT-d spec
541  * User needs to understand the Intel VT-d specification to decode the
552  * struct iommu_hw_info_arm_smmuv3 - ARM SMMUv3 hardware information
557  * @idr: Implemented features for ARM SMMU Non-secure programming interface
573  * - S1P should be assumed to be true if a NESTED HWPT can be created
574  * - VFIO/iommufd only support platforms with COHACC, it should be assumed to be
576  * - ATS is a per-device property. If the VMM describes any devices as ATS
594  * enum iommu_hw_info_type - IOMMU Hardware Info Types
597  * @IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info type
629  * struct iommu_hw_info - ioctl(IOMMU_GET_HW_INFO)
635  * @data_uptr: User pointer to a user-space buffer used by the kernel to fill
650  * a guest stage-1 page table can be compatible with the physical iommu.
674  * enum iommufd_hwpt_set_dirty_tracking_flags - Flags for steering dirty
683  * struct iommu_hwpt_set_dirty_tracking - ioctl(IOMMU_HWPT_SET_DIRTY_TRACKING)
701  * enum iommufd_hwpt_get_dirty_bitmap_flags - Flags for getting dirty bits
714  * struct iommu_hwpt_get_dirty_bitmap - ioctl(IOMMU_HWPT_GET_DIRTY_BITMAP)
747  * enum iommu_hwpt_invalidate_data_type - IOMMU HWPT Cache Invalidation
758  * enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d
759  *                                           stage-1 cache invalidation
761  *                            to all-levels page structure cache or just
769  * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
777  * The Intel VT-d specific invalidation data for user-managed stage-1 cache
779  * tell the impacted cache scope after modifying the stage-1 page table.
794  * struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cache invalidation
796  * @cmd: 128-bit cache invalidation command that runs in SMMU CMDQ.
797  *       Must be little-endian.
809  * -EIO will be returned if the command is not supported.
816  * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE)
819  * @data_uptr: User pointer to an array of driver-specific cache invalidation
825  * @entry_num: Input the number of cache invalidation requests in the array.
826  *             Output the number of requests successfully handled by kernel.
829  * Invalidate iommu cache for user-managed page table or vIOMMU. Modifications
830  * on a user-managed page table should be followed by this operation, if a HWPT
834  * Each ioctl can support one or more cache invalidation requests in the array
853  * enum iommu_hwpt_pgfault_flags - flags for struct iommu_hwpt_pgfault
864  * enum iommu_hwpt_pgfault_perm - perm bits for struct iommu_hwpt_pgfault
881  * struct iommu_hwpt_pgfault - iommu page fault data
891  *          transfer, it could fill in 10MB and the OS could pre-fault in
893  * @cookie: kernel-managed cookie identifying a group of fault messages. The
910  * enum iommufd_page_response_code - Return status of fault handlers
924  * struct iommu_hwpt_page_response - IOMMU page fault response
925  * @cookie: The kernel-managed cookie reported in the fault message.
934  * struct iommu_fault_alloc - ioctl(IOMMU_FAULT_QUEUE_ALLOC)
951  * enum iommu_viommu_type - Virtual IOMMU Type
961  * struct iommu_viommu_alloc - ioctl(IOMMU_VIOMMU_ALLOC)
970  * virtualization support that is a security-isolated slice of the real IOMMU HW
973  * - Security namespace for guest owned ID, e.g. guest-controlled cache tags
974  * - Non-device-affiliated event reporting, e.g. invalidation queue errors
975  * - Access to a sharable nesting parent pagetable across physical IOMMUs
976  * - Virtualization of various platforms IDs, e.g. RIDs and others
977  * - Delivery of paravirtualized invalidation
978  * - Direct assigned invalidation queues
979  * - Direct assigned interrupts
992  * struct iommu_vdevice_alloc - ioctl(IOMMU_VDEVICE_ALLOC)
998  *           of AMD IOMMU, and vRID of a nested Intel VT-d to a Context Table
1013  * struct iommu_ioas_change_process - ioctl(VFIO_IOAS_CHANGE_PROCESS)
1034  * enum iommu_veventq_flag - flag for struct iommufd_vevent_header
1042  * struct iommufd_vevent_header - Virtual Event Header for a vEVENTQ Status
1049  * +----------------------+-------+----------------------+-------+---+-------+
1051  * +----------------------+-------+----------------------+-------+---+-------+
1055  * 1, it means that delta - 1 number of vEVENTs has lost, e.g. two lost vEVENTs:
1057  * +-----+----------------------+-------+----------------------+-------+-----+
1059  * +-----+----------------------+-------+----------------------+-------+-----+
1065  * +--+----------------------+-------+-----------------------------------------+
1067  * +--+----------------------+-------+-----------------------------------------+
1075  * enum iommu_veventq_type - Virtual Event Queue Type
1085  * struct iommu_vevent_arm_smmuv3 - ARM SMMUv3 Virtual Event
1087  * @evt: 256-bit ARM SMMUv3 Event record, little-endian.
1089  *       - 0x04 C_BAD_STE
1090  *       - 0x06 F_STREAM_DISABLED
1091  *       - 0x08 C_BAD_SUBSTREAMID
1092  *       - 0x0a C_BAD_CD
1093  *       - 0x10 F_TRANSLATION
1094  *       - 0x11 F_ADDR_SIZE
1095  *       - 0x12 F_ACCESS
1096  *       - 0x13 F_PERMISSION
1106  * struct iommu_veventq_alloc - ioctl(IOMMU_VEVENTQ_ALLOC)
1124  * a type-specific data structure, in a normal case:
1126  * +-+---------+-------+---------+-------+-----+---------+-------+-+
1128  * +-+---------+-------+---------+-------+-----+---------+-------+-+