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33 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
59 #define KVM_SREGS_E_IMPL_FSL	1
61 #define KVM_SREGS_E_FSL_PIDn	(1 << 0) /* PID1/PID2 */
65 #define   KVM_RUN_PPC_NMI_DISP_FULLY_RECOV	(1 << 0)
77  * CSRR0/1 (refers to SRR2/3 on 40x)
87 #define KVM_SREGS_E_BASE		(1 << 0)
93  * MCSRR0/1
97 #define KVM_SREGS_E_ARCH206		(1 << 1)
103 #define KVM_SREGS_E_64			(1 << 2)
105 #define KVM_SREGS_E_SPRG8		(1 << 3)
106 #define KVM_SREGS_E_MCIVPR		(1 << 4)
112 #define KVM_SREGS_E_IVOR		(1 << 5)
116  * Also TLBnPS if MMUCFG[MAVN] = 1.
118 #define KVM_SREGS_E_ARCH206_MMU		(1 << 6)
121 #define KVM_SREGS_E_DEBUG		(1 << 7)
123 /* Enhanced debug -- DSRR0/1, SPRG9 */
124 #define KVM_SREGS_E_ED			(1 << 8)
127 #define KVM_SREGS_E_SPE			(1 << 9)
133 #define KVM_SREGS_EXP			(1 << 10)
136 #define KVM_SREGS_E_PD			(1 << 11)
139 #define KVM_SREGS_E_PC			(1 << 12)
142 #define KVM_SREGS_E_PT			(1 << 13)
145 #define KVM_SREGS_E_PM			(1 << 14)
161 #define KVM_SREGS_E_UPDATE_MCSR		(1 << 0)
162 #define KVM_SREGS_E_UPDATE_TSR		(1 << 1)
163 #define KVM_SREGS_E_UPDATE_DEC		(1 << 2)
164 #define KVM_SREGS_E_UPDATE_DBSR		(1 << 3)
289 #define KVMPPC_DEBUG_BREAKPOINT		(1UL << 1)
290 #define KVMPPC_DEBUG_WATCH_WRITE	(1UL << 2)
291 #define KVMPPC_DEBUG_WATCH_READ		(1UL << 3)
329 #define KVM_INTERRUPT_SET	-1U
333 #define KVM_CPU_440		1
384 	 *   TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1)
432 #define KVM_PPC_MMUV3_RADIX	1	/* 1 = radix mode, 0 = HPT */
457 #define KVM_PPC_CPU_CHAR_SPEC_BAR_ORI31		(1ULL << 63)
458 #define KVM_PPC_CPU_CHAR_BCCTRL_SERIALISED	(1ULL << 62)
459 #define KVM_PPC_CPU_CHAR_L1D_FLUSH_ORI30	(1ULL << 61)
460 #define KVM_PPC_CPU_CHAR_L1D_FLUSH_TRIG2	(1ULL << 60)
461 #define KVM_PPC_CPU_CHAR_L1D_THREAD_PRIV	(1ULL << 59)
462 #define KVM_PPC_CPU_CHAR_BR_HINT_HONOURED	(1ULL << 58)
463 #define KVM_PPC_CPU_CHAR_MTTRIG_THR_RECONF	(1ULL << 57)
464 #define KVM_PPC_CPU_CHAR_COUNT_CACHE_DIS	(1ULL << 56)
465 #define KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST	(1ull << 54)
467 #define KVM_PPC_CPU_BEHAV_FAVOUR_SECURITY	(1ULL << 63)
468 #define KVM_PPC_CPU_BEHAV_L1D_FLUSH_PR		(1ULL << 62)
469 #define KVM_PPC_CPU_BEHAV_BNDS_CHK_SPEC_BAR	(1ULL << 61)
470 #define KVM_PPC_CPU_BEHAV_FLUSH_COUNT_CACHE	(1ull << 58)
487 #define KVM_DEV_MPIC_GRP_MISC		1
678 #define KVM_DEV_XICS_GRP_SOURCES	1	/* 64-bit source attributes */
680 #define   KVM_DEV_XICS_NR_SERVERS	1
687 #define  KVM_XICS_LEVEL_SENSITIVE	(1ULL << 40)
688 #define  KVM_XICS_MASKED		(1ULL << 41)
689 #define  KVM_XICS_PENDING		(1ULL << 42)
690 #define  KVM_XICS_PRESENTED		(1ULL << 43)
691 #define  KVM_XICS_QUEUED		(1ULL << 44)
694 #define KVM_DEV_XIVE_GRP_CTRL		1
695 #define   KVM_DEV_XIVE_RESET		1
704 #define KVM_XIVE_LEVEL_SENSITIVE	(1ULL << 0)
705 #define KVM_XIVE_LEVEL_ASSERTED		(1ULL << 1)
740 #define KVM_PPC_PVINFO_FLAGS_EV_IDLE   (1<<0)