Lines Matching full:power

211 #define  PCI_CAP_ID_PM		0x01	/* Power Management */
236 /* Power Management Registers */
243 #define  PCI_PM_CAP_AUX_POWER	0x01C0	/* Auxiliary power support mask */
244 #define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
245 #define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
255 #define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
263 #define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
498 #define  PCI_EXP_DEVCAP_PWR_IND	0x00004000 /* Power Indicator Present */
500 #define  PCI_EXP_DEVCAP_PWR_VAL	0x03fc0000 /* Slot Power Limit Value */
501 #define  PCI_EXP_DEVCAP_PWR_SCL	0x0c000000 /* Slot Power Limit Scale */
518 #define  PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
533 #define  PCI_EXP_DEVSTA_AUXPD	0x0010	/* AUX Power Detected */
550 #define  PCI_EXP_LNKCAP_CLKPM	0x00040000 /* Clock Power Management */
590 #define  PCI_EXP_SLTCAP_PCP	0x00000002 /* Power Controller Present */
593 #define  PCI_EXP_SLTCAP_PIP	0x00000010 /* Power Indicator Present */
596 #define  PCI_EXP_SLTCAP_SPLV	0x00007f80 /* Slot Power Limit Value */
597 #define  PCI_EXP_SLTCAP_SPLS	0x00018000 /* Slot Power Limit Scale */
603 #define  PCI_EXP_SLTCTL_PFDE	0x0002	/* Power Fault Detected Enable */
613 #define  PCI_EXP_SLTCTL_PIC	0x0300	/* Power Indicator Control */
614 #define  PCI_EXP_SLTCTL_PWR_IND_ON     0x0100 /* Power Indicator on */
615 #define  PCI_EXP_SLTCTL_PWR_IND_BLINK  0x0200 /* Power Indicator blinking */
616 #define  PCI_EXP_SLTCTL_PWR_IND_OFF    0x0300 /* Power Indicator off */
617 #define  PCI_EXP_SLTCTL_PCC	0x0400	/* Power Controller Control */
618 #define  PCI_EXP_SLTCTL_PWR_ON         0x0000 /* Power On */
619 #define  PCI_EXP_SLTCTL_PWR_OFF        0x0400 /* Power Off */
622 #define  PCI_EXP_SLTCTL_ASPL_DISABLE	0x2000 /* Auto Slot Power Limit Disable */
626 #define  PCI_EXP_SLTSTA_PFD	0x0002	/* Power Fault Detected */
720 #define PCI_EXT_CAP_ID_PWR	0x04	/* Power Budgeting */
738 #define PCI_EXT_CAP_ID_DPA	0x16	/* Dynamic Power Allocation */
851 /* Power Budgeting */
854 #define  PCI_PWR_DATA_BASE(x)	((x) & 0xff)	    /* Base Power */
859 #define  PCI_PWR_DATA_RAIL(x)	(((x) >> 18) & 7)   /* Power Rail */
907 #define HT_CAPTYPE_PM		0xE0	/* HyperTransport power management configuration */
1028 /* Dynamic Power Allocation */