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41 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
42 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
43 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
44 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
46 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
47 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
48 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
49 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
162 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
164 #define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */
199 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
200 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
257 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
263 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
327 #define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
408 #define PCI_EA_ENABLE 0x80000000 /* Enable for this entry */
418 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
419 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
505 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
506 #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
508 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
516 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
517 #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
518 #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
519 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
557 #define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */
558 #define PCI_EXP_LNKCTL_ASPM_L1 0x0002 /* L1 Enable */
564 #define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */
566 #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */
567 #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Link Autonomous Bandwidth Interrupt Enable */
602 #define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */
603 #define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */
604 #define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */
605 #define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */
606 #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */
607 #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
621 #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */
638 #define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
639 #define PCI_EXP_RTCTL_RRS_SVE 0x0010 /* Config RRS Software Visibility Enable */
678 #define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */
679 #define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 /* Enable OBFF Message type A */
680 #define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */
796 #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
798 #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
804 #define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */
805 #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
806 #define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */
897 #define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */
917 #define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
918 #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
928 #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
935 #define PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */
952 #define PCI_PASID_CTRL_ENABLE 0x0001 /* Enable bit */
953 #define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */
954 #define PCI_PASID_CTRL_PRIV 0x0004 /* Privilege Mode Enable */
962 #define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */
963 #define PCI_SRIOV_CTRL_VFM 0x0002 /* VF Migration Enable */
964 #define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */
965 #define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */
1057 #define PCI_TPH_CTRL_REQ_EN_MASK 0x00000300 /* TPH Requester Enable */
1073 #define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */
1074 #define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */
1075 #define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */
1109 #define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */
1123 #define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */
1124 #define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */
1125 #define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */
1126 #define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */
1146 #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
1168 #define PCI_NPEM_CTRL_ENABLE 0x00000001 /* NPEM Enable */
1203 #define PCI_DOE_CTRL_INT_EN 0x00000002 /* DOE Interrupt Enable */