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38 * further describe the buffer's format - for example tiling or compression.
41 * ----------------
55 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * may preserve meaning - such as number of planes - from the fourcc code,
63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
75 * - Kernel and user-space drivers: for drivers it's important that modifiers
79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
92 * -----------------------
97 * upstream in-kernel or open source userspace user does not apply.
221 * IEEE 754-2008 binary16 half-precision float
231 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
247 …1010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only…
251 * 16-xx padding occupy lsb
259 * 16-xx padding occupy lsb except Y410
284 * 1-plane YUV 4:2:0
287 * These formats can only be used with a non-Linear modifier.
294 * index 0 = RGB plane, same format as the corresponding non _A8 format has
317 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
318 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
326 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
363 /* 3 plane non-subsampled (444) YCbCr
371 /* 3 plane non-subsampled (444) YCrCb
396 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) plane…
397 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) plane…
403 * Format modifiers describe, typically, a re-ordering or modification
407 * The upper 8 bits of the format modifier are a vendor-id as assigned
428 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
448 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
450 * compatibility, in cases where a vendor-specific definition already exists and
455 * generic layouts (such as pixel re-ordering), which may have
456 * independently-developed support across multiple vendors.
459 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
486 * which tells the driver to also take driver-internal information into account
496 * used is out-of-band information carried in an API-specific way (e.g. in a
504 * Intel X-tiling layout
507 * in row-major layout. Within the tile bytes are laid out row-major, with
508 * a platform-dependent stride. On top of that the memory can apply
509 * platform-depending swizzling of some higher address bits into bit6.
513 * cross-driver sharing. It exists since on a given platform it does uniquely
514 * identify the layout in a simple way for i915-specific userspace, which
521 * Intel Y-tiling layout
524 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
525 * chunks column-major, with a platform-dependent height. On top of that the
526 * memory can apply platform-depending swizzling of some higher address bits
531 * cross-driver sharing. It exists since on a given platform it does uniquely
532 * identify the layout in a simple way for i915-specific userspace, which
539 * Intel Yf-tiling layout
541 * This is a tiled layout using 4Kb tiles in row-major layout.
542 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
543 * are arranged in four groups (two wide, two high) with column-major layout.
545 * out as 2x2 column-major.
557 * The main surface will be plane index 0 and must be Y/Yf-tiled,
574 * Intel color control surfaces (CCS) for Gen-12 render compression.
576 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
580 * Y-tile widths.
585 * Intel color control surfaces (CCS) for Gen-12 media compression
587 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
591 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
598 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
601 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
619 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
640 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
681 * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
710 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
722 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
732 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
734 * Macroblocks are laid in a Z-shape, and each pixel data is following the
739 * - multiple of 128 pixels for the width
740 * - multiple of 32 pixels for the height
742 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
747 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
749 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
759 * Implementation may be platform and base-format specific.
772 * Implementation may be platform and base-format specific.
785 * Implementation may be platform and base-format specific.
795 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
801 * Vivante 64x64 super-tiling layout
803 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
804 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
808 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
813 * Vivante 4x4 tiling layout for dual-pipe
817 * compared to the non-split tiled layout.
822 * Vivante 64x64 super-tiling layout for dual-pipe
824 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
826 * therefore halved compared to the non-split super-tiled layout.
831 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
883 * ---- ----- -----------------------------------------------------------------
887 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
889 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
891 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
893 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
901 * 11:9 - Reserved (To support 2D-array textures with variable array stride
922 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
923 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
933 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
949 * 55:25 - Reserved for future use. Must be zero.
961 * with block-linear layouts, is remapped within drivers to the value 0xfe,
962 * which corresponds to the "generic" kind used for simple single-sample
963 * uncompressed color formats on Fermi - Volta GPUs.
980 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
1023 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
1025 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
1034 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
1037 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1040 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
1044 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
1045 * tiles) or right-to-left (odd rows of 4k tiles).
1068 * and UV. Some SAND-using hardware stores UV in a separate tiled
1109 * number of banks, and XOR address, and that it's identical between
1112 * the assumption is that a no-XOR tiling modifier will be created.
1120 * It provides fine-grained random access and minimizes the amount of data
1125 * and different devices or use-cases may support different combinations.
1157 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1174 * AFBC block-split
1195 * AFBC copy-block restrict
1197 * Buffers with this flag must obey the copy-block restriction. The restriction
1198 * is such that there are no copy-blocks referring across the border of 8x8
1218 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1224 * AFBC double-buffer
1226 * Indicates that the buffer is allocated in a layout safe for front-buffer
1234 * Indicates that the buffer includes per-superblock content hints.
1251 * Arm Fixed-Rate Compression (AFRC) modifiers
1255 * reductions in graphics and media use-cases.
1271 * ---------------- ---------------
1282 * ------ ----------------- ------------------
1291 * ----------------------------- --------- ----------------- ------------------
1294 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1295 * ----------------------------- --------- ----------------- ------------------
1298 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1299 * ----------------------------- --------- ----------------- ------------------
1301 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1302 * ----------------------------- --------- ----------------- ------------------
1305 * ----------------------------- --------- ----------------- ------------------
1324 * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1329 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1331 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1333 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1347 * Indicates if the buffer uses the scanline-optimised layout
1348 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1354 * Arm 16x16 Block U-Interleaved modifier
1373 * both in row-major order.
1387 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1389 * - DRM_FORMAT_YUV420_8BIT
1390 * - DRM_FORMAT_YUV420_10BIT
1414 * - a body content organized in 64x32 superblocks with 4096 bytes per
1416 * - a 32 bytes per 128x64 header block
1434 * be accessible by the user-space clients, but only accessible by the
1437 * The user-space clients should expect a failure while trying to mmap
1438 * the DMA-BUF handle returned by the producer.
1459 * ----- ------------------------ ---------------------------------------------
1479 * Bits 8-15 specify compression options
1486 * Bits 16-23 specify how the bits of 10 bit formats are
1498 * Apple GPU-tiled layouts.
1502 * GPU-tiled images are divided into 16KiB tiles:
1505 * --------------- ---------
1512 * Tiles are raster-order. Pixels within a tile are interleaved (Morton order).
1514 * Compressed images pad the body to 128-bytes and are immediately followed by a
1516 * powers-of-two and contains 8 bytes for each 16x16 compression subtile.
1519 * All images are 128-byte aligned.
1536 * https://docs.mesa3d.org/drivers/asahi.html#image-layouts
1547 * - main surface
1550 * - main surface in plane 0
1551 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1554 * - main surface in plane 0
1555 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1556 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1558 * For multi-plane formats the above surfaces get merged into one plane for
1562 * ----- ------------------------ ---------------------------------------------
1578 * 55:36 - Reserved for future use, must be zero
1598 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1601 * 64K_D_2D on GFX12 is identical to 64K_D on GFX11.
1611 * 0 - LINEAR
1612 * 1 - 256B_2D - 2D block dimensions
1613 * 2 - 4KB_2D
1614 * 3 - 64KB_2D
1615 * 4 - 256KB_2D
1616 * 5 - 4KB_3D - 3D block dimensions
1617 * 6 - 64KB_3D
1618 * 7 - 256KB_3D
1640 * one which is not-aligned.