standard-headers/drm/drm_fourcc.h

112 /* color index */
554  * Intel color control surface (CCS) for render compression
574  * Intel color control surfaces (CCS) for Gen-12 render compression.
585  * Intel color control surfaces (CCS) for Gen-12 media compression
598  * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
602  * and at index 1. The clear color is stored at index 2, and the pitch should
603  * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits
604  * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
605  * by 32 bits. The raw clear color is consumed by the 3d engine and generates
606  * the converted clear color of size 64 bits. The first 32 bits store the Lower
607  * Converted Clear Color value and the next 32 bits store the Higher Converted
608  * Clear Color value when applicable. The Converted Clear Color values are
609  * consumed by the DE. The last 64 bits are used to store Color Discard Enable
628  * Intel color control surfaces (CCS) for DG2 render compression.
638  * Intel color control surfaces (CCS) for DG2 media compression.
650  * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
656  * clear color is stored at plane index 1 and the pitch should be 64 bytes
657  * aligned. The format of the 256 bits of clear color data matches the one used
664  * Intel Color Control Surfaces (CCS) for display ver. 14 render compression.
675  * Intel Color Control Surfaces (CCS) for display ver. 14 media compression
688  * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render
692  * and at index 1. The clear color is stored at index 2, and the pitch should
693  * be ignored. The clear color structure is 256 bits. The first 128 bits
694  * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
695  * by 32 bits. The raw clear color is consumed by the 3d engine and generates
696  * the converted clear color of size 64 bits. The first 32 bits store the Lower
697  * Converted Clear Color value and the next 32 bits store the Higher Converted
698  * Clear Color value when applicable. The Converted Clear Color values are
699  * consumed by the DE. The last 64 bits are used to store Color Discard Enable
707  * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
719  * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
832  * the color buffer tiling modifiers defined above. When TS is present it's a
834  * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer
963  * uncompressed color formats on Fermi - Volta GPUs.
1216  * AFBC solid color blocks
1218  * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1219  * can be reduced if a whole superblock is a single color.
1658  * However, on older GPUs the rendering HW ignores the embedded clear color
1659  * and prefers the driver provided color. This necessitates doing a fastclear