Lines Matching full:1
74 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
77 #define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
99 #define ICH9_CC_GCS_NO_REBOOT (1 << 5)
106 /* D29:F0 USB UHCI Controller #1 */
164 #define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4)
179 /* D31:F2 SATA Controller #1 */
188 #define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
198 #define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
199 #define ICH9_PMIO_SMI_EN_SWSMI_EN (1 << 6)
200 #define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13)
201 #define ICH9_PMIO_SMI_EN_PERIODIC_EN (1 << 14)
203 #define ICH9_PMIO_SMI_STS_SWSMI_STS (1 << 6)
204 #define ICH9_PMIO_SMI_STS_PERIODIC_STS (1 << 14)
222 #define ICH9_SMB_SMBM_SIZE (1 << 8)
225 #define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
227 #define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
228 #define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
229 #define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
230 #define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
248 #define ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT 1