Lines Matching +full:0 +full:x62
80 #define ICH9_CC_D28IP 0x310C
82 #define ICH9_CC_D28IP_MASK 0xf
83 #define ICH9_CC_D28IP_DEFAULT 0x00214321
84 #define ICH9_CC_D31IR 0x3140
85 #define ICH9_CC_D30IR 0x3142
86 #define ICH9_CC_D29IR 0x3144
87 #define ICH9_CC_D28IR 0x3146
88 #define ICH9_CC_D27IR 0x3148
89 #define ICH9_CC_D26IR 0x314C
90 #define ICH9_CC_D25IR 0x3150
91 #define ICH9_CC_DIR_DEFAULT 0x3210
92 #define ICH9_CC_D30IR_DEFAULT 0x0
94 #define ICH9_CC_DIR_MASK 0x7
95 #define ICH9_CC_OIC 0x31FF
96 #define ICH9_CC_OIC_AEN 0x1
97 #define ICH9_CC_GCS 0x3410
98 #define ICH9_CC_GCS_DEFAULT 0x00000020
101 /* D28:F[0-5] */
108 #define ICH9_USB_UHCI1_FUNC 0
112 #define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
115 #define ICH9_D2P_BRIDGE_FUNC 0
119 #define ICH9_D2P_A2_REVISION 0x92
122 #define ICH9_RST_CNT_IOPORT 0xCF9
126 #define ICH9_A2_LPC_SAVEVM_VERSION 0
129 #define ICH9_LPC_FUNC 0
131 #define ICH9_A2_LPC_REVISION 0x2
134 #define ICH9_LPC_PMBASE 0x40
136 #define ICH9_LPC_PMBASE_RTE 0x1
137 #define ICH9_LPC_PMBASE_DEFAULT 0x1
139 #define ICH9_LPC_ACPI_CTRL 0x44
140 #define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
141 #define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ICH9_MASK(8, 2, 0)
142 #define ICH9_LPC_ACPI_CTRL_9 0x0
143 #define ICH9_LPC_ACPI_CTRL_10 0x1
144 #define ICH9_LPC_ACPI_CTRL_11 0x2
145 #define ICH9_LPC_ACPI_CTRL_20 0x4
146 #define ICH9_LPC_ACPI_CTRL_21 0x5
147 #define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
149 #define ICH9_LPC_PIRQA_ROUT 0x60
150 #define ICH9_LPC_PIRQB_ROUT 0x61
151 #define ICH9_LPC_PIRQC_ROUT 0x62
152 #define ICH9_LPC_PIRQD_ROUT 0x63
154 #define ICH9_LPC_PIRQE_ROUT 0x68
155 #define ICH9_LPC_PIRQF_ROUT 0x69
156 #define ICH9_LPC_PIRQG_ROUT 0x6a
157 #define ICH9_LPC_PIRQH_ROUT 0x6b
159 #define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
160 #define ICH9_LPC_PIRQ_ROUT_MASK ICH9_MASK(8, 3, 0)
161 #define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
163 #define ICH9_LPC_GEN_PMCON_1 0xa0
165 #define ICH9_LPC_GEN_PMCON_2 0xa2
166 #define ICH9_LPC_GEN_PMCON_3 0xa4
167 #define ICH9_LPC_GEN_PMCON_LOCK 0xa6
169 #define ICH9_LPC_RCBA 0xf0
171 #define ICH9_LPC_RCBA_EN 0x1
172 #define ICH9_LPC_RCBA_DEFAULT 0x0
190 #define ICH9_PMIO_PM1_STS 0x00
191 #define ICH9_PMIO_PM1_EN 0x02
192 #define ICH9_PMIO_PM1_CNT 0x04
193 #define ICH9_PMIO_PM1_TMR 0x08
194 #define ICH9_PMIO_GPE0_STS 0x20
195 #define ICH9_PMIO_GPE0_EN 0x28
197 #define ICH9_PMIO_SMI_EN 0x30
202 #define ICH9_PMIO_SMI_STS 0x34
205 #define ICH9_PMIO_TCO_RLD 0x60
209 #define ICH9_APM_ACPI_ENABLE 0x2
210 #define ICH9_APM_ACPI_DISABLE 0x3
216 #define ICH9_A2_SMB_REVISION 0x02
217 #define ICH9_SMB_PI 0x00
219 #define ICH9_SMB_SMBMBAR0 0x10
220 #define ICH9_SMB_SMBMBAR1 0x14
221 #define ICH9_SMB_SMBM_BAR 0
223 #define ICH9_SMB_SMB_BASE 0x20
226 #define ICH9_SMB_HOSTC 0x40
230 #define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
236 #define ICH9_SMB_HST_STS 0x00
237 #define ICH9_SMB_HST_CNT 0x02
238 #define ICH9_SMB_HST_CMD 0x03
239 #define ICH9_SMB_XMIT_SLVA 0x04
240 #define ICH9_SMB_HST_D0 0x05
241 #define ICH9_SMB_HST_D1 0x06
242 #define ICH9_SMB_HOST_BLOCK_DB 0x07
247 #define ICH9_LPC_SMI_F_BROADCAST_BIT 0