Lines Matching full:end
55 * Event Notifification Descriptor (END)
111 #define xive2_end_is_valid(end) (be32_to_cpu((end)->w0) & END2_W0_VALID) argument
112 #define xive2_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END2_W0_ENQUEUE) argument
113 #define xive2_end_is_notify(end) \ argument
114 (be32_to_cpu((end)->w0) & END2_W0_UCOND_NOTIFY)
115 #define xive2_end_is_backlog(end) (be32_to_cpu((end)->w0) & END2_W0_BACKLOG) argument
116 #define xive2_end_is_precluded_escalation(end) \ argument
117 (be32_to_cpu((end)->w0) & END2_W0_PRECL_ESC_CTL)
118 #define xive2_end_is_escalate(end) \ argument
119 (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_CTL)
120 #define xive2_end_is_uncond_escalation(end) \ argument
121 (be32_to_cpu((end)->w0) & END2_W0_UNCOND_ESCALATE)
122 #define xive2_end_is_silent_escalation(end) \ argument
123 (be32_to_cpu((end)->w0) & END2_W0_SILENT_ESCALATE)
124 #define xive2_end_is_escalate_end(end) \ argument
125 (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_END)
126 #define xive2_end_is_firmware1(end) \ argument
127 (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE1)
128 #define xive2_end_is_firmware2(end) \ argument
129 (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE2)
130 #define xive2_end_is_ignore(end) \ argument
131 (be32_to_cpu((end)->w6) & END2_W6_IGNORE)
132 #define xive2_end_is_crowd(end) \ argument
133 (be32_to_cpu((end)->w6) & END2_W6_CROWD)
135 static inline uint64_t xive2_end_qaddr(Xive2End *end) in xive2_end_qaddr() argument
137 return ((uint64_t) be32_to_cpu(end->w2) & END2_W2_EQ_ADDR_HI) << 32 | in xive2_end_qaddr()
138 (be32_to_cpu(end->w3) & END2_W3_EQ_ADDR_LO); in xive2_end_qaddr()
141 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf);
142 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width,
144 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
157 #define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */
192 * field of the XIVE END. When running in Gen1 mode (P9 compat mode),