Lines Matching +full:- +full:- +full:enable +full:- +full:fdt

4  * Copyright (c) 2014-2016 BenH, IBM Corporation.
29 #define TYPE_PNV_CHIP "pnv-chip"
37 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
83     void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
122 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
133     (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
138     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
142     (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
149  * 30     : 1 to enable ICP to receive loads/stores against its BAR region
154  *      0xffffe00200000000 -> 0x0003ffff80000000
155  *      0xffffe00600000000 -> 0x0003ffff80100000
156  *      0xffffe02200000000 -> 0x0003ffff80800000
157  *      0xffffe02600000000 -> 0x0003ffff80900000
161     (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE)
166     (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE)
170     (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \
177     ((base) + ((uint64_t) (chip)->chip_id << 42))
206     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
209     (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
212  * POWER10 MMIO base addresses - 16TB stride per chip
215     ((base) + ((uint64_t) (chip)->chip_id << 44))
250     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
253     (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)