Lines Matching defs:CadenceGEMState

47 struct CadenceGEMState {  struct
49     SysBusDevice parent_obj;
52     MemoryRegion iomem;
53     MemoryRegion *dma_mr;
54     AddressSpace dma_as;
55     NICState *nic;
56     NICConf conf;
57     qemu_irq irq[MAX_PRIORITY_QUEUES];
60     uint8_t num_priority_queues;
61     uint8_t num_type1_screeners;
62     uint8_t num_type2_screeners;
63     uint32_t revision;
64     uint16_t jumbo_max_len;
67     uint32_t regs[CADENCE_GEM_MAXREG];
69     uint32_t regs_wo[CADENCE_GEM_MAXREG];
71     uint32_t regs_ro[CADENCE_GEM_MAXREG];
73     uint32_t regs_rtc[CADENCE_GEM_MAXREG];
75     uint32_t regs_w1c[CADENCE_GEM_MAXREG];
78     uint8_t phy_addr;
80     uint16_t phy_regs[32];
82     uint8_t phy_loop; /* Are we in phy loopback? */
85     uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES];
86     uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES];
88     uint8_t can_rx_state; /* Debug only */
90     uint8_t tx_packet[MAX_FRAME_SIZE];
91     uint8_t rx_packet[MAX_FRAME_SIZE];
92     uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS];
94     bool sar_active[4];