Lines Matching +full:bool +full:- +full:property

14  * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
16  * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
24  * The MSC has no register interface -- it is configured purely by a
26  * they are either hardwired or exposed in an ad-hoc register interface by
39  * + Named GPIO output "irq": set for a transaction-failed interrupt
40  * + Property "downstream": MemoryRegion defining where bus master transactions
42  * + Property "idau": an object implementing IDAUInterface, which defines which
43  *   addresses should be treated as secure and which as non-secure.
57 #define TYPE_TZ_MSC "tz-msc"
67     bool cfg_nonsec;
68     bool cfg_sec_resp;
69     bool irq_clear;
71     bool irq_status;