Lines Matching full:18

108  *  18:16  MAC AHB bus clock divider selection
124  *  18     H-PLL parameter selection
136 #define SCU_AST2400_H_PLL_PROGRAMMED               (0x1 << 18)
146  *  18:13  H-PLL Post Divider
169  * 23,18  Clock source selection
202 /* bit 23, 18 [1,0] */
204                                                     | (((x) & 0x1) << 18))
206                                                     | (((x) >> 18) & 0x1))
207 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK       ((0x1 << 23) | (0x1 << 18))
214 #define SCU_HW_STRAP_CLK_48M_IN                    (0x1 << 18)
278  * 18     Select USBCKI input frequency
308 #define SCU_AST2500_HW_STRAP_USBCKI_FREQ           (0x1 << 18)
344  *  18:13  H-PLL Numerator (M)
388  *  20:18  PCLK_DIV
405 #define SCUIO_AST2700_CLK_GET_PCLK_DIV(x)                    (((x) >> 18) & 0x7)