Lines Matching +full:10 +full:m

112  *  10:8   Video port output clock delay control bit
129  *  10:5   H-PLL Numerator
147  *  12:5   H-PLL Numerator (M)
150  *  (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
175  * 11:10  CPU/AHB clock frequency ratio selection
227 #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x)  ((x) << 10)
228 #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x)  (((x) >> 10) & 3)
229 #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK    (0x3 << 10)
344  *  18:13  H-PLL Numerator (M)
347  *  (Output frequency) = CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1)
393  *  10     UART11CLK_SEL