Lines Matching defs:AwR40DramCtlState

68 struct AwR40DramCtlState {  struct
70     SysBusDevice parent_obj;
74     hwaddr ram_addr;
77     uint32_t ram_size;
79     uint8_t set_row_bits;
80     uint8_t set_bank_bits;
81     uint8_t set_col_bits;
87     MemoryRegion dramcom_iomem;    /**< DRAMCOM module I/O registers */
88     MemoryRegion dramctl_iomem;    /**< DRAMCTL module I/O registers */
89     MemoryRegion dramphy_iomem;    /**< DRAMPHY module I/O registers */
90     MemoryRegion dram_high;        /**< The high 1G dram for dualrank detect */
91     MemoryRegion detect_cells;     /**< DRAM memory cells for auto detect */
100     uint32_t dramcom[AW_R40_DRAMCOM_REGS_NUM]; /**< DRAMCOM registers */
101     uint32_t dramctl[AW_R40_DRAMCTL_REGS_NUM]; /**< DRAMCTL registers */
102     uint32_t dramphy[AW_R40_DRAMPHY_REGS_NUM] ;/**< DRAMPHY registers */