hw/intc/arm_gicv3_common.h

11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation, either version 2 of the License, or
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  * You should have received a copy of the GNU General Public License along
32  * Maximum number of possible interrupts, determined by the GIC architecture.
42  * The redistributor in GICv3 has two 64KB frames per CPU; in
55  * For some distributor fields we want to model the array of 32-bit
57  * pending, etc bits. We use the set_bit32() etc family of functions
62  * space for the PPIs and SGIs, those bits (the first 32) are never
63  * used as that state lives in the redistributor. The unused bits are
80 /* Return a pointer to the 32-bit word containing the specified bit. */
91  * (where the latter two are exposed as a single banked system register).
92  * In the state struct they are implemented as a 3-element array which
93  * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants.
94  * If the CPU doesn't support EL3 then the G1 element is unused.
96  * These constants are also used to communicate the group to use for
97  * an interrupt or SGI when it is passed between the cpu interface and
98  * the redistributor or distributor. For those purposes the receiving end
101  * independently in the CPU and in the GIC. In that case the receiver should
103  * (This architectural requirement is why the _G1 element is the unused one
105  * between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.)
113  * (If the CPU or the GIC, respectively, don't support the Security
114  * extensions then the S element is unused.)
174     /* Properties of the CPU interface. These are initialized from
175      * the settings in the CPU proper.
176      * If the number of implemented list registers is 0 then the
186      * This is cached information that can be recalculated from the
204      * Whether the CPU interface has NMI support (FEAT_GICv3_NMI). The
205      * CPU interface may support NMIs even when the GIC proper (what the
206      * spec calls the IRI; the redistributors and distributor) does not.
212  * The redistributor pages might be split into more than one region
249     /* for a GIC with the security extensions the NS banked version of this
250      * register is just an alias of bit 1 of the S banked version.
264     /* Cached information: pointer to the cpu i/f for the CPUs specified
265      * in the IROUTER registers
324  * in use. May throw an error if the chosen implementation is not available.