Lines Matching defs:GICv3CPUState

87 typedef struct GICv3CPUState GICv3CPUState;  typedef
126 struct GICv3CPUState {  struct
127     GICv3State *gic;
128     CPUState *cpu;
129     qemu_irq parent_irq;
130     qemu_irq parent_fiq;
131     qemu_irq parent_virq;
132     qemu_irq parent_vfiq;
133     qemu_irq parent_nmi;
134     qemu_irq parent_vnmi;
137     uint32_t level;                  /* Current IRQ level */
139     uint32_t gicr_ctlr;
140     uint64_t gicr_typer;
141     uint32_t gicr_statusr[2];
142     uint32_t gicr_waker;
143     uint64_t gicr_propbaser;
144     uint64_t gicr_pendbaser;
146     uint32_t gicr_igroupr0;
147     uint32_t gicr_ienabler0;
148     uint32_t gicr_ipendr0;
149     uint32_t gicr_iactiver0;
150     uint32_t gicr_inmir0;
151     uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */
152     uint32_t gicr_igrpmodr0;
153     uint32_t gicr_nsacr;
154     uint8_t gicr_ipriorityr[GIC_INTERNAL];
156     uint64_t gicr_vpropbaser;
157     uint64_t gicr_vpendbaser;
160     uint64_t icc_sre_el1;
161     uint64_t icc_ctlr_el1[2];
162     uint64_t icc_pmr_el1;
163     uint64_t icc_bpr[3];
164     uint64_t icc_apr[3][4];
165     uint64_t icc_igrpen[3];
166     uint64_t icc_ctlr_el3;
169     uint64_t ich_apr[3][4]; /* ich_apr[GICV3_G1][x] never used */
170     uint64_t ich_hcr_el2;
171     uint64_t ich_lr_el2[GICV3_LR_MAX];
172     uint64_t ich_vmcr_el2;
179     int num_list_regs;
180     int vpribits; /* number of virtual priority bits */
181     int vprebits; /* number of virtual preemption bits */
182     int pribits; /* number of physical priority bits */
183     int prebits; /* number of physical preemption bits */
189     PendingIrq hppi;
195     PendingIrq hpplpi;
198     PendingIrq hppvlpi;
201     bool seenbetter;
208     bool nmi_support;