hw/i386/intel_iommu.h

2  * QEMU emulation of an Intel IOMMU (VT-d)
25 #include "hw/i386/x86-iommu.h"
26 #include "qemu/iova-tree.h"
29 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
32 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
49 #define VTD_HAW_MASK(aw)            ((1ULL << (aw)) - 1)
67 /* Context-Entry */
116      * The tree is not needed if no MAP notifier is registered with current
121      * The tree OTOH is required for MAP typed iommu notifiers for a few
124      * Firstly, there's no way to identify whether an PSI (Page Selective
126      * MAP or UNMAP event within the message itself.  Without having prior
128      * notify MAP or UNMAP for a PSI message it received when caching mode
129      * is enabled (for MAP notifiers).
137      * registered drivers (e.g. vfio-pci) on either:
139      *   (1) Trying to map the same region more than once (for
140      *       VFIO_IOMMU_MAP_DMA, -EEXIST will trigger), or,
144      * That accuracy is not required for UNMAP-only notifiers, but it is a
145      * must-to-have for notifiers registered with MAP events, because the
162 /* VT-d Source-ID Qualifier types */
167     VTD_SQ_IGN_1_3 = 0x03,  /* Ignore bits 1-3 */
171 /* VT-d Source Validation Types */
173     VTD_SVT_NONE = 0x00,    /* No validation */
211         uint64_t sid_vtype:2;        /* Source-ID Validation Type */
212         uint64_t sid_q:2;            /* Source-ID Qualifier */
213         uint64_t source_id:16;       /* Source-ID */
215         uint64_t source_id:16;       /* Source-ID */
216         uint64_t sid_q:2;            /* Source-ID Qualifier */
217         uint64_t sid_vtype:2;        /* Source-ID Validation Type */
227 /* Programming format for MSI/MSI-X addresses */
232         uint32_t index_l:15;         /* Interrupt index bit 14-0 */
234         uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
240         uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
242         uint32_t index_l:15;         /* Interrupt index bit 14-0 */
249 /* When IR is enabled, all MSI/MSI-X data bits should be zero */
262     uint8_t womask[DMAR_REG_SIZE];  /* WO (write only - read returns 0) */
265     bool caching_mode;              /* RO - is cap CM enabled? */
266     bool scalable_mode;             /* RO - is Scalable Mode supported? */
267     bool flts;                      /* RO - is stage-1 translation supported? */
268     bool snoop_control;             /* RO - is SNP filed supported? */
283      * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
311     bool fs1gp;                     /* First Stage 1-GByte Page Support */
318      * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.