hw/i386/intel_iommu.h

253 struct IntelIOMMUState {  struct
254     X86IOMMUState x86_iommu;
255     MemoryRegion csrmem;
256     MemoryRegion mr_nodmar;
257     MemoryRegion mr_ir;
258     MemoryRegion mr_sys_alias;
259     uint8_t csr[DMAR_REG_SIZE];     /* register values */
260     uint8_t wmask[DMAR_REG_SIZE];   /* R/W bytes */
261     uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
262     uint8_t womask[DMAR_REG_SIZE];  /* WO (write only - read returns 0) */
263     uint32_t version;
265     bool caching_mode;              /* RO - is cap CM enabled? */
266     bool scalable_mode;             /* RO - is Scalable Mode supported? */
267     bool flts;                      /* RO - is stage-1 translation supported? */
268     bool snoop_control;             /* RO - is SNP filed supported? */
270     dma_addr_t root;                /* Current root table pointer */
271     bool root_scalable;             /* Type of root table (scalable or not) */
272     bool dmar_enabled;              /* Set if DMA remapping is enabled */
274     uint16_t iq_head;               /* Current invalidation queue head */
275     uint16_t iq_tail;               /* Current invalidation queue tail */
276     dma_addr_t iq;                  /* Current invalidation queue pointer */
277     uint16_t iq_size;               /* IQ Size in number of entries */
278     bool iq_dw;                     /* IQ descriptor width 256bit or not */
279     bool qi_enabled;                /* Set if the QI is enabled */
280     uint8_t iq_last_desc_type;      /* The type of last completed descriptor */
285     uint16_t next_frcd_reg;
287     uint64_t cap;                   /* The value of capability reg */
288     uint64_t ecap;                  /* The value of extended capability reg */
290     uint32_t context_cache_gen;     /* Should be in [1,MAX] */
291     GHashTable *iotlb;              /* IOTLB */
293     GHashTable *vtd_address_spaces;             /* VTD address spaces */
294     VTDAddressSpace *vtd_as_cache[VTD_PCI_BUS_MAX]; /* VTD address space cache */
298     GHashTable *vtd_host_iommu_dev;             /* HostIOMMUDevice */
301     bool intr_enabled;              /* Whether guest enabled IR */
302     dma_addr_t intr_root;           /* Interrupt remapping table pointer */
326 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus,  argument