hw/cxl/cxl_device.h

63 /* CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register */
67  * CXL r3.1 Section 8.2.8.2.1: CXL Device Capabilities +
68  * CXL r3.1 Section 8.2.8.5: Memory Device Capabilities
76  * CXL r3.1 Section 8.2.8.3: Device Status Registers
212     /* CXL r3.1 Section 8.2.8.3: Device Status Registers */
232     /* CXL r3.1 Section 8.2.8.4: Mailbox Registers */
274  * CXL r3.1 Section 8.2.8.1: CXL Device Capabilities Array Register
289  * In CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register, this is
290  * listed as a 128b register, but in CXL r3.1 Section 8.2.8: CXL Device Register
292  * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that
353 /* CXL r3.2 Section 8.2.8.3.1: Event Status Register */
359 /* CXL r3.1 Section 8.2.8.4.3: Mailbox Capabilities Register */
368 /* CXL r3.1 Section 8.2.8.4.4: Mailbox Control Register */
374 /* CXL r3.1 Section 8.2.8.4.5: Command Register */
380 /* CXL r3.1 Section 8.2.8.4.6: Mailbox Status Register */
386 /* CXL r3.1 Section 8.2.8.4.7: Background Command Status Register */
393 /* CXL r3.1 Section 8.2.8.4.8: Command Payload Registers */
396 /* CXL r3.1 Section 8.2.8.4.1: Memory Device Status Registers */