hw/arm/armsse.h

8  * it under the terms of the GNU General Public License version 2 or
13  * This is a model of the Arm "Subsystems for Embedded" family of
14  * hardware, which include the IoT Kit and the SSE-050, SSE-100 and
16  *  - the Arm IoT Kit which is documented in
18  *  - the SSE-200 which is documented in
21  * The IoTKit contains:
23  *  the IDAU
28  *  a bus fabric which arranges that some parts of the address
30  * The SSE-200 additionally contains:
42  *  + QOM property "memory" is a MemoryRegion containing the devices provided
43  *    by the board model.
44  *  + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
45  *    (In hardware, the SSE-200 permits the number of expansion interrupts
46  *    for the two CPUs to be configured separately, but we restrict it to
47  *    being the same for both, to avoid having to have separate Property
50  *  + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the
51  *    address of each SRAM bank (and thus the total amount of internal SRAM)
52  *  + QOM property "init-svtor" sets the initial value of the CPU SVTOR register
53  *    (where it expects to load the PC and SP from the vector table on reset)
55  *    set whether the CPUs have the FPU and DSP features present. The default
56  *    (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
58  *    Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
60  *    which set the number of MPU regions on the CPUs. If there is only one
61  *    CPU the CPU1 properties are not present.
62  *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
64  *  + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
66  *  + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows
67  *    bus master devices in the board model to make transactions into
68  *    all the devices and memory areas in the IoTKit
69  * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit
76  * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
83  * Controlling each of the 16 expansion MPCs which a system using the IoTKit
86  * Controlling each of the 16 expansion MSCs which a system using the IoTKit
125  * them via the ARMSSE base class, so they have no IOTKIT() etc macros.
132  * and the 2 internal PPCs
147 /* Number of CPU IRQs used by the SSE itself */
191      * 'cpu_container[i]' is the view that CPU i has: this has the
192      * per-CPU devices of that CPU, plus as the background 'container'
194      * container_alias[i] is the alias of 'container' used by CPU i+1;